采用Verilog HDL设计，在Altera EP1S10S780C6开发板上实现 选取6MHz为基准频率，演奏的是梁祝乐曲 - Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang

EP1S10S780C6开发板上实现选取6MHz为基准频率，演奏梁祝乐曲,使用Verilog HDL设计的源码.-EP1S10S780C6 selected to achieve the development board as the base frequency of 6MHz, playing music Butterfly Lovers, the use of Verilog HDL design source.