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DPRAM
- 网络控制器和链路控制器的CPU即是通过读写双端口RAM芯片完成网络层与数据链路层的原语交互。mailbox中写入的是原语的类型，而双端口RAM的其它存储空间则存放各种服务原语的参数。-network controller and the CPU controller link is through reading and writing dual-port RAM chip to complete the network layer a
双口RAM硬件和软件可靠性握手的实现
- 双口RAM硬件和软件可靠性握手的实现 双口RAM硬件和软件可靠性握手的实现-dual-port RAM reliability of the hardware and software to shake hands with the dual port RAM hardware and software to achieve the reliability handshake
allidt_20020616.tar
- idt的双口ram的读写接口程序，verilog 代码，并且有测试文档-Employing a dual-port ram reader interface program, Verilog code, and a test document
vhdl_ad0809_arm
- 本程序是用VHDL语言写的，包括AD0809，双口RAM等程序。已经调试过-this program is written in VHDL, including the AD0809, dual-port RAM, and other procedures. Debugging has been too
danpianji3
- SH601.C 单片机间的RS232串行通信程序 SH602.C 单片机和PC之间的串行通信程序 SH603.A51 用51单片机的I/O口模拟串口的例程 SH604.C 单片机的无线数据传输例程 SH605.A51 使用单片机实现I2C串行通信的例程 SH606.A51 使用单片机实现的红外数据传输 SH607.C 双端口RAM方式的数据通信例程 608 介绍电平转换芯片MAX485的使用方法和接口电路。
dualportRAM
- 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
128×16ram
- VHDL程序设计的RAM存储器，双端口，128×16比特-VHDL programming RAM memory, dual-port, 128 × 16 bits
Asynchronous_read_write_RAM
- Dual Port RAM Asynchronous Read/Write 经过modelsim仿真 -Dual Port RAM Asynchronous Read/Write through ModelSim Simulation
dul_ram(yk)
- 关于双口RAM的Verilog HDL源码-On the dual-port RAM in Verilog HDL source
dev
- linux下 双口ram驱动程序 2.4.18-linux under the dual-port ram driver 2.4.18
fifov1
- FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用 双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、 与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data） 为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO
dualporttst-1_0
- xilinx 开发板原程序，双口RAM控制-Xilinx development board the original procedures, dual-port RAM control
doubleportram
- 高速双端口RAM的vhdl实现。包含仿真波形-High-speed dual-port RAM realize the VHDL. Contains the simulation waveform
DPRAM
- 利用vhdl编写的双端口Ram程序，不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction
RAM
- 双口RAM的应用-Application of dual-port RAM
13
- para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
RAM
- 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
ASYNCFIFOXPXMOD
- 任意时钟配比的异步fifo.含有synplify ip库中的双端口ram。用于处理多时钟域问题。-Arbitrary ratio of asynchronous clock fifo. Containing synplify ip library of dual-port ram. Used to deal with the issue of multi-clock domain.
ram_of_Fusion
- Fusion中的双口RAM编写，可以实现双向的调用。用Verilog编写。-Fusion in the preparation of dual-port RAM, you can realize a two-way call. Prepared using Verilog.
dual-ram
- 实现双口RAM映射到DSP地址单元空间中，使得双口RAM直接读取DSP中的数据或程序。-Achieve dual-port RAM modules mapped to the DSP address space, making dual-port RAM directly read the data in the DSP or procedures.