搜索资源列表
Digital_Clock
- 数字时钟:LCD+凌阳SPCEO61A,通过中断计时,LCD显示,界面简洁宜人-Digital Clock : LCD Sunplus SPCEO61A through interruption time, LCD display, Pleasant simple interface
digital_clock
- 用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者-verlog language with a good addendum to the comprehensive experiment, particularly suitable for FPGA / CPLD beginners
digital_clock
- 基于AT89S52的自动报时数字闹钟. 该数字钟具有整点报时和闹钟功能，时间显示为 时.分.秒，以12小时制显示。可通过按键调整时间的小时位和分钟位，整点和闹钟均以闪烁方式报时。 程序分为以下模块：数码管显示模块，控制显示模块，定时器T0中断处理模块，定时器T1中断处理模块，键盘扫描模块，键盘处理模块，延时模块和整点闪烁模块
Digital_Clock-7Seg
- Digital Clock Source using ATmega8515 and 7Segment
digital_clock
- 用veriolg写的数字钟实验，具有定点报时，闰年判断，年月日显示，下载平台为spantan3s400。有详细注解。适合verilog学习
digital_clock
- 单片机源代码,数字实时钟,C源码,KEIL C开发环境.
Digital_Clock
- 数字时钟:LCD+凌阳SPCEO61A,通过中断计时,LCD显示,界面简洁宜人-Digital Clock : LCD Sunplus SPCEO61A through interruption time, LCD display, Pleasant simple interface
digital_clock
- 用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者-verlog language with a good addendum to the comprehensive experiment, particularly suitable for FPGA/CPLD beginners
digital_clock
- 基于AT89S52的自动报时数字闹钟. 该数字钟具有整点报时和闹钟功能，时间显示为 时.分.秒，以12小时制显示。可通过按键调整时间的小时位和分钟位，整点和闹钟均以闪烁方式报时。 程序分为以下模块：数码管显示模块，控制显示模块，定时器T0中断处理模块，定时器T1中断处理模块，键盘扫描模块，键盘处理模块，延时模块和整点闪烁模块-AT89S52 based on automatic timekeeping digital alarm
Digital_Clock-7Seg
- Digital Clock Source using ATmega8515 and 7Segment
digital_clock
- 用veriolg写的数字钟实验，具有定点报时，闰年判断，年月日显示，下载平台为spantan3s400。有详细注解。适合verilog学习-Written by veriolg digital clock experiments with fixed time, to determine leap year, date display, download platform spantan3s400. Have a detailed an
digital_clock
- 单片机源代码,数字实时钟,C源码,KEIL C开发环境.-Single-chip source code, the number of real-time clock, C source, KEIL C development environment.
digital_clock
- 基于C语言编程的keil单片机有关数学时钟的设计，比起汇编，C语言更具简洁性-Based on C language programming keil Singlechip clock on the mathematical design, compared to the compilation, C language is more concise and
Digital_Clock
- 使用汇编语言实现数字时钟设计，用7seg完成显示，并可以通过button对时钟进行调整。并包括系统仿真原理图，适合做设计者使用-The use of assembly language to achieve digital clock design, with the completion of 7seg show, and can adjust the button on the clock. And includes system
c51.digital_clock
- 一个单片机80c51数字时钟设计，含电路原理图-A digital clock 80C51 single-chip design, including circuit schematics
Digital_Clock
- 用7seg来模拟平时看的最多的电子表，分别有小时--分钟--秒-use 7seg to simulate digital clock,show hour--minute--second
digital_clock
- 实现嵌入式系统的秒表计时，时间显示和闹钟功能-Implementation of embedded systems stopwatch timer, time display and alarm clock function
Digital_clock
- Qt实现的一个数字时钟，是一个dll，运行bat就可以生成工程文件，调试的时候可以改成EXE程序-Qt to achieve a digital clock is a dll, run the bat can be generated on the project file, when debugging process can be altered into EXE
digital_clock
- 数字钟vhdl程序，能够显示年月日，时分秒，还有闰年-digital_clock.It can show the year,month,day and so on.