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DIVIDER
- 除法器，这是一个简单的除法器，虽然位数不是很长，但是可以通过这个程序延伸-divider, which is a simple divider, while the median is not very long, but it extends through this procedure
divider.rar
- A divider implemented in VHDL
数字钟的设计
- 数字式计时器一般都由震荡器，分频器，译码器及显示几部分组成。其中震荡器和分频器组成标准秒信号发生器，接成各种不同进制的计数器组成计时系统，译码器，显示器组成显示系统，另外一些组合电路组成校时调节系统。-digital timer usually are oscillator, dividers, decoder and display several parts. Which oscillator and divider standar
DIVIDER
- 除法器，这是一个简单的除法器，虽然位数不是很长，但是可以通过这个程序延伸-divider, which is a simple divider, while the median is not very long, but it extends through this procedure
VHDL5
- 加法器 乘法器电路 除法器电路设计 键盘扫描电路设计 显示电路-Adder multiplier circuit divider circuit design keyboard scan circuit design show circuit, etc.
7_Rsa
- RSA公钥加密算法基于大整数因式分解困难这样的事实。 选择两个素数，p，q。（一般p,q选择很大的数） 然后计算 z=p*q f=(p-1)(q-1) 选择一个n，使gcd(n,f)=1（gcd代表greatest common divider,一般n也选择一个素数）， n和z就作为公钥。 选择一个s,0<s<f,满足n*s ％ f=1，s就作为私钥。-RSA public key encryption alg
Verilog_FPGA_fp
- 用Verilog实现基于FPGA的通用分频器-using Verilog FPGA-based Universal Frequency Divider
odd_divider_VHDL
- 常用1、3、5及任意奇数分频器的VHDL代码实现（原创）-used 1,3,5 and arbitrary odd Divider VHDL code to achieve (original)
VHDLEXAMPLEppt
- 介绍8位加法器、分频电路、数字秒表的PPT，带源码，解释详细，一步一步学习，是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learnin
divider
- 一个用VHDL语言编写的除法器程序，对从事硬件开发的同志有帮助的。-A language using VHDL divider procedures comrades engaged in hardware development have help.
divider
- 介绍了除法器的设计，采用verilogHDL语言，利用modelsim仿真验证，压缩包中包含了流程图-Introduced the divider design, using verilogHDL language, the use of ModelSim simulation, compressed package that contains a flow chart
divider
- 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。-This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-poi
divider
- 经过精心设计的除法器的代码，并在FPGA硬件平台实现和验证过的-Meticulously designed divider code, and FPGA hardware platform and tested
divider
- 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit inte
divider
- 移位快速除法器，通过一次移4位试商实现快速除法功能，较普通减除法器有及其巨大的效率提升-Divider rapid shift by a shift to four test functions of rapid division, as compared with ordinary objects have less efficiency and its huge
divider
- 基于Verilog的除法器设计，可以直接在Q2里面运行哦~-Verilog-based design of the divider, which can be run directly in Q2 Oh ~
divider
- 8位的除法器。用VHDL语言进行设计实现。-8-bit divider. With VHDL design languages.
divider
- a clock divider vhdl code
divider
- verilog divider hardware
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.