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Verilog DHL教程.zip
- Verilog DHL教程
Verilog DHL数字钟
- 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
suif1_3_rh8
- c到DHL的转换工具，适合用Ｃ语言编的算法在FPGA上做加速处理．
sc2_1.1beta.tar
- c到DHL的转换工具，适合用Ｃ语言编的算法在FPGA上做加速处理．
sc2_1.3beta.tar
- c到DHL的转换工具，适合用Ｃ语言编的算法在FPGA上做加速处理．
sc2_1.2beta.tar
- c到DHL的转换工具，适合用Ｃ语言编的算法在FPGA上做加速处理．
java 实现 ftp 客户端cz.hdl库的源码
- ............\cz ............\..\dhl ............\..\...\ftp ............\..\...\...\Ftp.java ............\..\...\...\FtpConnect.java ............\..\...\...\FtpContext.java ............\..\...\...\Ftp
Verilog DHL教程
- Verilog DHL教程-Verilog DHL course
Verilog DHL数字钟
- 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
suif1_3_rh8
- c到DHL的转换工具，适合用Ｃ语言编的算法在FPGA上做加速处理．-c to DHL conversion tools for C language made use of the algorithm in FPGA to do to speed up processing.
sc2_1.1beta.tar
- c到DHL的转换工具，适合用Ｃ语言编的算法在FPGA上做加速处理．-c to DHL conversion tools for C language made use of the algorithm in FPGA to do to speed up processing.
sc2_1.3beta.tar
- c到DHL的转换工具，适合用Ｃ语言编的算法在FPGA上做加速处理．-c to DHL conversion tools for C language made use of the algorithm in FPGA to do to speed up processing.
sc2_1.2beta.tar
- c到DHL的转换工具，适合用Ｃ语言编的算法在FPGA上做加速处理．-c to DHL conversion tools for C language made use of the algorithm in FPGA to do to speed up processing.
digital-clock
- 该数字钟论文是我用了一周的时间，采用Verilog DHL语言设计， Quratuse8.1仿真通过的文章-This paper is a digital clock I used a week, Verilog by DHL language design, Quratuse8.1 simulation through the article
arm7verilog
- ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
Sdifferhl1V
- 矢量的合成分析 求矢量f(n,2)在指数x(n)为高指数年(x(n)>coefh的年）的平均值fh(2)、低指数年(x(n)<coefh的年）的平均值fl(2)、高指数年与气候平均的合成差dh(2)、低指数年与气候平均的合成差dl(2)、以及高低指数年的合成差dhl(2)和差的显著性tn(5)。 -Synthesis of vector demand vector f (n, 2) the index of x (n)
ff_const_mul
- 常系数有限域乘法器，verilog DHL源码-Constant coefficient finite field multiplier, verilog DHL source
X-HDL
- 一款可以在verilog和VHDL之间互换的工具，经测试，暂无bug-A verilog and VHDL can be exchanged between the tools, tested, no bug
ADDER
- verilog DHL编写的一位全加器，编译通过。稍作修改便可编程任意位加法器。-verilog DHL write a full adder, compiled by. Slight modifications can be programmed any adder.
AC PROJECT DHL DOC
- ac project source code for beginner