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DDR（双速率）SDRAM控制器参考设计verilog代码
- DDR SDRAM reference design documentation
DDR内存布线指导
- Freescale 发布的 DDR内存PCB布线指导
Xilinx spartan 6 DDR 测试源代码
- Xilinx FPGA Spartan 6 上可运行的软核microblaze以及外设DDR, SPI,UART等测试代码
ref-ddr-sdram-vhdl
- 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
ref-ddr-sdram-vhdl
- 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
ddr
- ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be r
cpu-leon3-altera-ep2s60-ddr
- 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
ddr
- davincievm 6446 記憶體DDR撿測-davincievm 6446 seized DDR memory test
DDR
- 关于DDR SDRAM的详细原理和时序分析,对于开发设计有很大使用价值-DDR SDRAM on detailed principles and timing analysis, design for the development of a great value
ref-ddr-sdram-vhdl
- 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
ddr
- 关于ddr sdram的一篇不错的文章，讲得挺详细的。-a good paper about ddr sdram，teaching you how to use ddr sdram.
wb-ddr
- 基于Wishbone总线的DDR控制器. -A wraper of DDR controller for wishbone bus.
ddr-sdram--chengxu
- ddr的控制程序，实用Verilog语言实现的非常的具体，非常无奈过的实用。-ddr
ddr-sdram
- DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
ddr
- 合众达DM6446试验箱学习实验源代码 ddr内存实验-the experimental source code DM6446 chamber ddr memory test
DDR
- DDR内存条的设计资料，PC1600 and PC 21-DDR memory design data, PC1600 and PC 2100
DDR
- 开发DDR很有价值得开发资料 希望对大家有点帮助 -Development of the developers of DDR valuable information we hope a little help
ddr
- 该程序是TI的达芬奇处理器DM6467开发板的DDR测试程序，该程序的开发环境是CCS3.3，使用的编程语言是C-The program is for TI s DaVinci processor DM6467 development board test program of DDR , the program s development environment is CCS3.3, using the programming lan
ddr
- DDR SDRAM 控制器 VHDL代码，可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus