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D触发器的设计
- D触发器的设计 主要用在时序电路中。 所用语言为Verilog HDL.-D flip-flop with the main design of the timing circuit. The language used for Verilog HDL.
d
- VHDL的D触发器,简明了
d
- d 触发器 简单的d触发器，上传仅供参考，望各位多多指教。
带同步清0、同步置1 的D 触发器
- 带同步清0、同步置1 的D 触发器, Verilog HDL 源码
D触发器的设计
- D触发器的设计 主要用在时序电路中。 所用语言为Verilog HDL.-D flip-flop with the main design of the timing circuit. The language used for Verilog HDL.
digital_trigger
- 数字电路学习：触发器原理演示，可自行设定工作状态，显示电路内部变化状态。-digital circuit Learning : Trigger principle demonstration can set their own working conditions, showing the internal circuit changes state.
dff_UDP
- verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过-verilog achieve, UDP asynchronous reset with a descr iption of the fringe is triggered D flip-flop, test test pass
dd
- 里用单片机、2个计数器以及D触发器对被测信号脉冲与标准信号脉冲利用单片机、2个计数器以及D触发器对被测信号脉冲与标准信号脉冲,同时计数，实现频率测量功能。在保证产品质量和提高产品功能的同时降低制作成本, 对产品进行简化设计。-Lane used microcontroller, two counters, as well as D flip-flop on the measured signal pulse with the stand
fffffff
- 里用单片机、2个计数器以及D触发器对被测信号脉冲与标准信号脉冲利用单片机、2个计数器以及D触发器对被测信号脉冲与标准信号脉冲,同时计数，实现频率测量功能。在保证产品质量和提高产品功能的同时降低制作成本, 对产品进行简化设计。-Lane used microcontroller, two counters, as well as D flip-flop on the measured signal pulse with the stand
Ddelay
- 在Quartus下使用D触发器来加入延迟，每个D触发器增加半个周期的延迟，稍加更改可以得到不同的延迟。-In Quartus using D flip-flop to join the delay, each D flip-flop raised a half-cycle delay, a little change can be a different delay.
def1
- 实现D触发器的基本功能,D触发器的功能是时钟信号为上升沿时检测输入信号并将其赋值给输出信号并维持到下一个上升沿(压缩包内为所有MAXPLUS2程序)-The realization of the basic functions of D flip-flop, D flip-flop function is when the clock signal for the rising edge detection of input signa
CPLD
- 本科教育的实体实例，其中包括3-8译码器，D触发器等逻辑模块，可以位初学CPLD的爱好者提供方便-Examples of undergraduate education entities, including the 3-8 decoder, D flip-flops and other logic modules, digital learning can facilitate fans CPLD
d
- VHDL的D触发器,简明了-VHDL of the D flip-flop, a concise
d
- d 触发器 简单的d触发器，上传仅供参考，望各位多多指教。-d of d simple flip-flop flip-flop, the upload is for reference only, hope that the exhibitions.
dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
my_reg
- D触发器，Verilog实现，配有实验说明文档。-D flip-flop, Verilog implementation, with experimental documentation.
dff1
- vhdl maxplus d触发器最基本的定义 自己看看有没有用-vhdl maxplus d trigger the most basic definition of their own to see if there is no use
Y_0D
- 带同步置1、异步清0的D触发器。详细的讲解，易懂。(D flip-flop with synchronous 1 and asynchronous clear 0. Detailed explanation, easy to understand.)
shiyanjiu
- 学习verilog时写的D触发器实验代码(D flip-flop experimental code written when learning Verilog)
shiyan9
- 学习verilog时写的D触发器源代码，供大家参考(D flip-flop experimental code written when learning Verilog)