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FPGA_ASIC-基于同步原则的FPGA-CPU设计.rar
- FPGA_ASIC-基于同步原则的FPGA-CPU设计.rar
simple_design_cpu
- 有是一个简单的cpu设计的开发过程！里面 有代码，和分析，设计过程！献给初学者的！-there is a simple design of the cpu development process! There are codes, and analysis, process design! Dedicated to beginners!
CPU_design
- 一个简单指令的cpu设计。 可以实现4个指令的的运算。-a simple instructions cpu design. 4 can be achieved directive arithmetic.
complexcpu_design
- 主要介绍一个很好的设计思想，介绍复杂cpu设计的框图。-introduces a very good design, introduced cpu design of complex diagram.
数字系统设计教程4_9
- vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design
riscdesign
- 一个非常简单的cpu设计的原代码,是用verilog编写的-a very simple cpu design of the original code, was prepared by the Verilog
good_CPU
- 本代码是在modelsim下运行的模拟8×8位的CPU，执行程度，对深入理解CPU设计和运行原理具有重要意义- This code is simulation 8脳8 position CPU which moves under modelsim, carries out the degree, to thoroughly understood the CPU design and the movement principle ha
MCUDesign
- 《Digital Logic And Microprocessor Design With VHDL》，CPU设计经典参考书-"Digital Logic And Microprocessor Design With VHDL, "CPU design classic reference books
8-CPU
- 简单的8位CPU，内含PDF文件.可自己查看详细说明-simple eight CPU, containing PDF files. They can check details
riscmcu
- 精简CPU设计，需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
cpupipeline
- CPU设计，加法器，乘法器，除法器等，有原理讲解等。挺不错的资料-CPU design, adders, multiplier, divider and so on and so have the principle. Very good information
RISC_Core.ZIP
- 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序-This is an 8-bit RISC CPU on the design of the article, which includes using the Verilog language CPU core procedures
comp_arith
- cpu设计中关于加法器，乘法器，除法器设计的ppt，希望对硬件学习的人有帮助-cpu design on the adder, multiplier, divider design ppt, want to learn hardware help
CPU
- 设计一个ＣＰＵ的具体过程，包括实验目的，逻辑图-CPU design a specific process, including experimental purposes, the logic diagram
cpu
- 本课程设计主要解决用CPLD芯片编程，实现基本模型机中的CPU功能。为方便地址显示灯观测，地址寄存器仍用试验装置上的电路单元，微程序控制器也用实验板上的单元电路提供，CPU的其余各个模块全部写入CPLD中。-This course is primarily designed to solve using CPLD chip programming, the realization of the basic model of the CP
mycpu
- Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。-Quartus II 5.0 written under a single bus architecture of the CPU design, including controllers, computing devices, su
controlunit
- CPU设计中的controlunit源码，其中附带了时序仿真。通过Sequencing Logic 产生 control_signals,具体的信号可在controlsignal.mif文件中直接修改。 -CPU design controlunit source, which comes with timing simulation. Sequencing Logic generated through control_signals
cpu
- 计算机组成原理假期课程设计“一个简单的CPU设计”，有全部的设计思路，能够实现四条简单指令-Principles of Computer Organization holidays curriculum design
CPU
- CPU 设计，不错的哦，顶一下哈，希望大家都弄成免费的-CPU design, good Oh, the top click Kazakhstan, I hope we all have to face free
CPU
- 基于ARM指令集自主进行CPU设计体验，第一版(Independent CPU design experience based on ARM instruction set, first edition)