搜索资源列表
AXIprotocol
- AMBA AXI Protocol Specification
AMBA
- SystemC写的AMBA 3.0 AXI总线事物级TLM模型 正在调试。有详细实验报告说明。-AMBA 3.0 AXI TLM SystemsC
USB2.0
- USB2.0行为级描述，挂接在AMBA AXI总线上-USB2.0 RTL discr iption
BP062-BU-01000-r0p0-00rel0[1][1].tar
- AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
System_Design_and_Implementation_of_AXI_Bus
- AMBA AXI资料，台湾硕士论文，网上收集-AMBA AXI, Taiwanese master' s thesis, on-line collection of
AMBAaxi
- AXI spcialification document
AMBA-AXI
- ARM 内核总线的介绍。学习一下可以更加容易掌握ARM的知识-ARM core-bus introduction. And study how to more easily grasp the knowledge of ARM
AMBA_axi_classic_protocol_document
- AMBA axi经典协议文档值得参考学习的资料AMBA axi classic protocol document-AMBA axi protocol documentation is also useful to study classical information AMBA axi classic protocol document
handshake
- AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
BP062
- This the AMBA® AXI Protocol v1.0 Source code-This is the AMBA® AXI Protocol v1.0 Source code
AMBAaxi
- AMBA axi bus protocol: the documents for implementing AMBA axi
AN151
- AMBA Application Note: AN151 - Using EB with example AXI Logic Tile. -AMBA Application Note: AN151- Using EB with example AXI Logic Tile. This example shows how to use the EB baseboard with an example AXI Logic
Axi_mux
- The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interf
ppt
- 介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
Micrium_Microblaze_uCOS-II-AXI
- 支持xilinx ise designer 14.x的microblaze AXI总线 ucosii操作系统。-Support xilinx ise designer 14.x for microblaze AXI bus ucosii operating system
AMBA AXI and ACE Protocol Specification.pdf
- AMBA AXI and ACE Protocol Specification
AMBA 3 AXI Protocol Specification.pdf
- AMBA 3 AXI Specification
AXI-HP-ZYNQ
- 用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write D
AXI-full
- axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)
verilog-axi-master
- Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi