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C_16450_edit
- 16450异步通讯接口，ALDEC提供，修正版（由网友zhy修改，修正一些错误-16450 asynchronous communications interface, providing ALDEC, the revised version (from netizens. Changes amendments to some errors
VHDLaldec
- VHDL多媒体式教学资料（aldec公司)-VHDL teaching multimedia information (aldec company )...............
C_16450_edit
- 16450异步通讯接口，ALDEC提供，修正版（由网友zhy修改，修正一些错误-16450 asynchronous communications interface, providing ALDEC, the revised version (from netizens. Changes amendments to some errors
VHDLaldec
- VHDL多媒体式教学资料（aldec公司)-VHDL teaching multimedia information (aldec company )...............
ud12
- this project is counter 12 bit up/down in vhdl to aldec enviroment .
C8255
- 这是ALDEC公司的8255IP core，是用VHDL 语言写的，包括文档和代码-This is a ALDEC the company' s 8255IP core, is written in VHDL language, including the documentation and code
VERILOG-Simulation
- This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus us
multiplier fpga
- Multiplication of two numbers from 0 to 9. The first number is displayed on the HEX7 indicator, increases with the KEY3 button, and decreases with the KEY2 button, the second is displayed on the HEX5 indicator, inc