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aFifo
- verylog语言编程，为异步flipflop的程序。具有数据传输功能，数据位数可以用户设定
afifo
- FIFO 经过多次修改及上板调试 可放心使用 本人也在学习之中
afifo
- 异步fifo的verilog程序，含有测试平台
aFifo
- verylog语言编程，为异步flipflop的程序。具有数据传输功能，数据位数可以用户设定-verylog language programming for asynchronous Flipflop procedures. With a data transmission function, data can be user set the median
afifo
- FIFO 经过多次修改及上板调试 可放心使用 本人也在学习之中-FIFO after many changes and debugging can be assured the board, I also study the use of
SF_table_interface
- switch fabric部分代码: fabric和table management 的数据交换. Mac address 从afifo输入, 查询的结果:output port number 存于pfifo中-switch fabric part of the code: fabric and table management data exchange. Mac address from afifo input, the resul
aFifo
- This an implementation of an Asynchronous FIFO written in Verilog 2001.-This is an implementation of an Asynchronous FIFO written in Verilog 2001.
aFifo
- 異步FIFO試作,寫入與讀取資料的時脈不同,藉此程式來達成-Test for asynchronous FIFO, write and read information on a different clock to the program to achieve
afifo
- verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
aFifo
- 很好用的异步FIFO设计代码，和大家共享一下，这是我在一个美国的网站上找到的-Asynchronous FIFO design with good code, and share how this is an American site I found on
aFifo
- it is a vhdl source code for FIFO
aFifo.vhd.txt
- Async. FIFO for rtl coding and simulation
aFIFO
- 异步fifo代码。包含GrayCounter计数的算法代码-Asynchronous fifo code， contains GrayCounter counting code
afifo
- verilog HDL fifo , verilog HDL fifo , -verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,
aFIFO
- 实现了一个异步fifo功能的verilog模块-An asynchronous fifo function verilog module
aFifo
- Function : Asynchronous FIFO VHDL CODE
aFifo
- 异步fifo用verilog语言实现的完整代码，适用于数字前端的设计-This implementation is based on the article Asynchronous FIFO