搜索资源列表
8BIT
- 基于FPGA的8位乘法器代码,可以进行四象限乘法
8BIT
- 基于FPGA的8位乘法器代码,可以进行四象限乘法-FPGA-based 8-bit multiplier code, can be four-quadrant multiplication
8-bit
- 最基本的vhdl運算，採用8bit作乘法器，將兩串8bit的值輸入之後進行相乘-VHDL basic computing, the use of 8bit for the multiplier, will be the value of two strings of 8bit input multiplied after
mult_8b_for
- 本实验使用Verilog语言 通过FOR循环完成8bit乘法器功能，通过ISE仿真测试，可实现综合-Verilog language used in this experiment through the FOR cycle completed 8bit multiplier function, through the ISE simulation tests can be integrated
8bit-Shift-and-Adder--multiplier
- 8位乘法器，经移位相加算法来实现的，用的VHDL语言-8-bit multiplier, adding the algorithm to realize the shift of
FFT
- 本程序为FFT的一个蝶形运算单元，输入位4位，输出8位，由于乘法器的原因，分实部与虚部，输出也为实部虚部，对其进行组合可实现FFT变换，其中乘法器为快速的列阵乘法器。-FFT butterfly unit, the input bit 4bit output 8bit, due to the multiplier, divided into real and imaginary parts, the output for the rea
booth_mul
- 流水式BOOTH乘法器，包含整个工程文件，用Quartus9编写打开。为8bit乘以8bit乘法器-Flow BOOTH multiplier, contains the entire project file, open with Quartus9 written. Multiplied for 8bit 8bit multiplier
8bit-multiplier
- 8位二进制数乘法器VHDL实现8位二进制数乘法器设计，乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。 -8-bit binary multiplier VHDL 8-bit binary multiplier design, multiplication by itemized shift sum principle, starting from
Hardware_Multiplier
- 利用MSP430F149内部的硬件乘法器进行8bit-8bit，16bit-16bit的乘法，只需三个主时钟周期，即可读出运算结果。-Using MSP430F149 internal hardware multiplier for 8bit-8bit, 16bit-16bit multiplication, just three master clock cycles, you can read out the result of t
ALU_finished
- 8bit四级流水ALU 其中有乘法器除法器加法器减法器开方 移位逻辑运算等等通过顶层来控制选择输出需要的运算值-8bit four water which has a multiplier divider ALU adder subtracter prescribing controlled shift logic operations so operators need to select the output value by th
8bit_multiplier
- 8bit 无符号串联乘法器，由状态机实现，用相加与移位实现乘法功能。-Unsigned 8bit serial multiplier, the state machine implementation, realized by adding the shift multiplication function.
multiplier_8bit_top
- 两个8bit无符号整数相乘，模块分为控制模块和数据路径(Two 8bit data multiplies)