搜索资源列表
clock_controller
- 89C2051 + 4-digit 7-SEG led + 4-key switch c源代码-89C2051 4-digit 7- SEG led 4-c switch key source
counter_7seg
- 带分频器的bcd计数电路设计,verilog源码-dividers with the bcd count circuit design, Verilog source
7seg
- 模擬微電腦設計-七段顯示器字型~~VB 模擬微電腦-七段顯示器字型做計時器的顯示 -Simulation microcomputer design- Seven-Segment Display Font ~ ~ VB simulation microcomputer- Seven-Segment display font to do the timer display
Digital_Clock
- 使用汇编语言实现数字时钟设计,用7seg完成显示,并可以通过button对时钟进行调整。并包括系统仿真原理图,适合做设计者使用-The use of assembly language to achieve digital clock design, with the completion of 7seg show, and can adjust the button on the clock. And includes system
7SEG
- 使用汇编语言编写的PIC小程序,实现7段数码管显示功能-it is a program written by asembly language,used to drive the 7-seg display numbers.
Seg7
- 这是关于七段码显示的基本程序,后面继续上传74HC595驱动七段数码管的驱动程序-7seg driver display
VoltageMeter
- AT89C52+ADC0809+Proteus仿真原理图,实现数字电压表-AT89C52+ ADC0809+ Proteus schematic simulation, digital voltage meter
7seg-led
- VHDL的彩灯程序,内含数码管和led灯的显示,按照各种循环方式一次显示-The Lantern VHDL program, containing the digital pipe and led lights are displayed, according to a variety of recycling methods show once again that
at89c51-7segBCD-asm
- 7SEG BCD 8051 in assembly language
at89c51-7SEGBCD-Schematics
- Schematics of 7SEG bcd counter 8051
7Seg---LED
- VHDL设计实验,实现VHDL设计控制交通灯-VHDL design of experiments, designed to control traffic lights to achieve VHDL
bcd-7seg
- Create a VHDL code representation of a BCD-to-Seven segment decoder. bcd 7 segment
BCD_to_7SEG
- BCD to 7-segment decoder
bcd
- 这是一个在vhdl中BCD的编程代码 为了可以让它更直观的表现出来 我们最后用7seg的方式 让其表示出来 把结果更加直观的呈现-This is a BCD in vhdl programming code in order to be able to make it more intuitive performance out of our way to let it finally 7seg represented more int
bcd-7seg
- bcd to 7segnments decoder in proteus
MTM_UEC1_lab04_raportfinalny
- verilog hdl BCD to 7seg converter with testing module
BCDTo7SEG
- This is a example for BCD to 7SEG. This code is wrote in VHDL
BCDto7seg
- bcd to 7 seg code in verilog
7447
- BCD to 7 seg with microcontroller AVR and simulation proteus file.