该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl cod

用VHDL语言实现64点的FFT,包含源程序和一篇论文-64-point FFT with VHDL contains the source code and a paper