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IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE
- IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
ieee-std-1364
- 做EDA的，就不用介绍这个文件了吧，IEEE1364标准（开放）。-done, would not have introduced the document on the bar, IEEE1364 standard (open).
IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE
- IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar-IEEE Std 1364.1-2002 IEEE Std. 1364.1- 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
ieee-std-1364
- 做EDA的，就不用介绍这个文件了吧，IEEE1364标准（开放）。-done, would not have introduced the document on the bar, IEEE1364 standard (open).
iir_par_code
- IIR code. IEEE STD 1364-1995 Verilog file: iir_par.v.
IEEEStd1364_2001
- verilog 1364——2001 语言标准-Verilog Hardware Descr iption Language standard
IEEE_Verilog_2001
- Verilog 2001 编程规范中文版，作为ASIC和FPGA逻辑开发人员学习不可多得的资料，也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
PalnitkarVerilogHDL
- Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspec
iverilog-0.9.2
- iverilog是verilog仿真综合工具，能够将verilog源代码编译为不同的目标文件-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format
Introduction-to-Verilog
- Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the
verilog-ieee.pdf.tar
- IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Descr iption Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at
Verilog-IEEE-Std(1364-2005)
- Verilog IEEE Std(1364-2005) 标准,硬件开发必备手册-Verilog IEEE Std (1364-2005) standards, hardware development of the necessary manual
Prentice---Verilog.HDL_A.Guide.to.Digital.Design.
- Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspec
cef_binary_3.1364.1094_windows
- cef3是支持多前程的google浏览器官方内核代码，其中有各种实例-cef3 support multiple future google browser official kernel code, including various instances
cef_binary_1.1364.1123_macosx
- cefMac是google开源浏览器针对苹果用户开发调用google浏览器的代码，里面有很多实例-cefMac call google browser google open source browser for Apple users to develop code, there are many examples
IEEE-Std-1364.1-2002-Verilog-RTL-Synthesys
- IEEE Std 1364.1-2002 Verilog RTL Synthesys
IEEE-Std-1364-2001-Verilog-LRM
- IEEE Std 1364-2001 Verilog LRM
IEEE_Verilog_2001
- IEEE 1364-2001 VerilogHDL IEEE 1364-2001 VerilogHDL
Dualx-master
- Dualx是一款基于Chrome的QQ客户端 您可以在使用基于版本为 25.0.1364.97 及以上的chromium内核的Chrome浏览器、Chrome OS操作系统及其他平台中使用。 Dualx使用WebQQ协议登录并与腾讯服务器进行通信，登录及通信过程只与*.qq.com域进行数据交换。 Dualx是开源的项目，遵循GPL协议发布（GPLv2 or later）。-QQ client Dualx is a client-b
GDW-1364-2013-
- GDW 1364-2013单相智能电能表技术规范-GDW 1364-2013single-phase intelligent watt-hour meter specification