用VHDL实现的加法器，可以进行减法运算，运算结果通过数码管显示，由于设计时的按键较少，所以运算的范围比较小，只能计算64以内的加减法运算，可以作为学习资料来参考。-Adder using VHDL implementation can be carried out subtraction, calculation resulted in the adoption of digital tube display, due to the

采用MAX+PlusII工具编辑设计的Verilog程序设计的简易加法器。可实现10以内的加法计算-Using MAX+PlusII tools to edit the design of Verilog design of a simple adder. Can be realized within 10 addition calculation

十以内的加法器，实现十以内的加法功能，最高位清零(en less than adder, to achieve the addition function within ten, the highest clear)