一个有效位为4位的十进制的数字频率计,VHDL语言编写，已在硬件实验箱上实验通过。-an effective place to four the number of decimal frequency meter, VHDL language, in the box on the experimental hardware experiment.

用Verilog HDL / VHDL实现的数字频率计（完整实验报告）-Using Verilog HDL/VHDL realization of digital frequency meter (complete test report)