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8bit全加器带进位复位功能
- 8bit全加器带进位复位功能 已经通过防真
8位二进制转化为2位BCD的PIC子程序
- 8位二进制转化为2位BCD的PIC子程序-eight binary into two BCD PIC Subroutine
Adnence_add8
- VHDL实现的超前进位加法器-the VHDL-ahead Adder
ADD_SUB
- 11,13,16位超前进位加法器的Verilog HDL源代码。-11,13,16-CLA for the Verilog HDL source code.
cla_vhd
- 超前进位加法器的例子,包括源码和测试文件,压缩包,无密码.-CLA of examples, including source code and test documents, compressed, without a password.
adder_ahead8bit
- 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
LAC_adder16
- 十六位超前进位加法器，Verilog HDL-16-ahead adder, Verilog HDL
CLA8
- 一个超前进位加法器的Verilog实现，内含测试文件，可以综合，非常有参考价值-A CLA of Verilog realize that contains the test documents, can be integrated and very useful
ahead_adder
- 用Verilog语言实现了一个8bit的超前进位加法器，其中包括测试文件。-Verilog language using an 8bit realize the CLA, including the test file.
CLA
- 超前进位加法器得VHDL实现小点资料代码-CLA was a small point of information VHDL code
adder
- 8位超前进位加法器 就是使各位的进位直接由加数和被加数来决定，而不需要依赖低位进位-8-bit CLA is to make your binary direct summand by summand and to decide, rather than to rely on low binary
VHDL_add_4
- 本程序完成带进位输入输出的四位二进制加法运算，编程思想采用真值表转换成布尔方程式，利用循环语句将一位全加器编为四位加法器。-This procedure is completed into the four-bit input and output binary adder computing, programming thinking of using truth table into a Boolean equation using
add2
- 两个4bit超前进位加法器实现8bit加法器-Two 4bit CLA realize 8bit adder
trueif
- 一个超前进位加法器（及其testbench) .v文件-A CLA (and its testbench). V file
56775
- VB6.0的2 8 16进位换算器-VB6.0 of 2 8 16 binary converter
adder
- 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
adder
- 进位加法，实现两个数的相加功能，可以扩展到多位数相加(Carry addition, to achieve the addition function of two numbers, can be extended to the number of add)
超前进位加法器
- 8*8超前进位加法器，Verilog初学教程(file name is adder.v adder 8*8 bit)
4Bit超前进位加法器门级电路设计与仿真
- 用门级网表的方法对4Bit超前进位加法器门级电路连接关系用verilog语言进行描述(The connection relation of the gate level circuit of 4Bit carry adder is described in Verilog language with the method of gate level netlist)
16位超前进位加法器
- 16位超前进位加法器的报告，报告里面含有主代码测试代码仿真结果(16 bit forward adder)