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秒表设计
- 用verilog hdl实现的秒表程序。可以精确计时到1分,可简单修改程序后实现更长时间的计时。
eclock
- MAXPULS II 下VHDL实现多功能电子钟的源代码,包括时钟,秒表,日历等多种功能-MAXPULS II under VHDL multifunctional electronic clock source code, including the clock, stopwatch, multiple functions such as calendar
NumClock
- 基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括:基本功能——以数字形式显示时、分、秒的时间,小时计数器为同步24进制,可手动校时、校分;扩展功能——仿广播电台正点报时,任意时刻闹钟(选做)
shuzimiaobiao
- 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
stop_watch
- 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
VERILOGMIAOBIAO
- 秒表计时器的verilog实现,是一个教授发表的学术论文。有点参考意义。-Stopwatch timer Verilog realize, is a professor of published academic papers. Somewhat useful.
wtut_ver
- verilog HDL语言编写的数字秒表,仿真已经通过,可供参考-verilog HDL language digital stopwatch, simulation has already been adopted, for reference
miaobiao
- 用Verilog HDL编写的秒表设计,可以实现百分之一秒,十分之一秒,秒,十秒等功能。-Verilog HDL prepared with a stopwatch designed to achieve the hundredth of a second, one-tenth of seconds, seconds, 10 seconds and other functions.
stopwatch
- Quartus II工程压缩文件,是一个典型的基于FPGA的秒表工程项目,有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
miaobiao
- 秒表功能,自带工程,EDA的设计平台QuartusⅡ-Stopwatch functions, bring their own works
StopWatch
- Verilog 编写的 秒表程序,在数码管上显示,带有清0和暂停键-Stopwatch Implemented by Verilog hdl
miaobiao
- 用VERILOG实现秒表的开发设计,(1)熟悉按键扫描、按键防抖和数码管驱动接口电路原理;(2)掌握按键扫描、按键防抖和数码管驱动接口电路设计开发;(3)掌握状态机实际应用设计。-To achieve the development of a stopwatch with VERILOG Design, (1) be familiar with key scanning, image stabilization and digital
clock
- 采用Verilog HDL语言编写的多功能数字钟,包括四个功能:时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings
watch
- 基于verilog-HDL的电子秒表电路,采用quartusII72编译仿真,经下载测试通过。-Verilog-HDL-based electronic stopwatch circuit simulation using quartusII72 compiled by downloading the test.
verilog
- 设计可以对两个运动员赛跑计时的秒表:(1)只有时钟(clk)和一个按键(key),每按一次,key是持续一个时钟周期的高电平脉冲 (2)秒表输出用0-59的整数表示 (3)key: (A)按一下key,开始计数; (B)第一个运动员到终点时第二下key,记住时间,继续计数; (C)二个运动员到时按第三下key,停止计数; (D)然后按第四下key,秒表输出第一个运动员到终点的时间,即按第二下key时记住的计数值;
stopwatch
- verilog 秒表程序 用quartus 编写-Verilog stopwatch ............................................................................................
key_display
- 秒表 verilog 程序非常适合刚接触 vreilog语言的人学习-Stopwatch verilog program is ideal for people new to vreilog language learning
verilog
- Verilog HDL 1.红外线发射调制电路 2.分数分频 3.最大公约数和最小公倍数 4.秒表-1.infra transmission modulator 2.fractal frequency divider 3.maximal common divisor 4.timer
miaobiao
- 秒表数码管实现,通过仿真验证,已下载到板子验证(The realization of the stopwatch digital tube)
Verilog秒表设计
- 用verilog在basys2开发板上实现一个具有置零、开始、暂停、记忆功能的秒表。(Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.)