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signalgenerater
- 一个简单的多种信号的发生器 包括正玄，锯齿，阶梯等，使用时用quartus 4.0以上版本打开-a simple multiple signal generator including Shogen, sawtooth, the ladder, when used with the above version 4.0 Quartus open
multiplex
- 复接程序,用quartus运行的,可以把很多个信号复接在一起,是程序的一部分!-Multiplexing procedures used quartus operations, can put a lot of signal multiplexing together, is part of that process.
用Quartus II对状态机进行功能仿真和时序仿真
- 用Quartus II对状态机进行功能仿真和时序仿真,不需要编写测试向量。文档附详细的操作步骤。
signalgenerater
- 一个简单的多种信号的发生器 包括正玄，锯齿，阶梯等，使用时用quartus 4.0以上版本打开-a simple multiple signal generator including Shogen, sawtooth, the ladder, when used with the above version 4.0 Quartus open
counter60
- 这是我们做的一个作业 摸60计数器，用Quartus ii 做的 ，内容齐全 不可不看。-This is the one we do feel 60 counter operation with Quartus ii do. complete contents can not see.
videofram
- 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image fr a me buffer cards logical verilog procedures, Quartus II 5.0 Open
Quartus_vhdl
- 用QUARTUS编译通过的等精度频率计，我错误，但有几个警告（不影响设计）。我的毕业设计啊！！！ -QUARTUS used by the compiler, and other precision frequency, I am wrong. But there are several warning (not affect design). I graduated from the design ah! ! !
uart
- VHDL编写的异步通信串行口设计用Quartus工具编译-VHDL prepared the design of serial asynchronous communication tool used Quartus compiler
Example-2-1
- 该程序是用quartus II作为开发工具，用verilog语言编写，实现helloworld的实例。对初学者很有意义-The program is used as a quartus II development tools, and Verilog languages, realize helloworld example. Meaningful for beginners
Time
- 24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
NIOS_TFT
- 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo fr a me, attached schematic and program code veri-log
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
IFFT(FPGA)
- 用QUARTUS软件开发，基于FPGA的IFFT处理器设计。-With QUARTUS software development, the IFFT processor based on FPGA design.
LVDS
- 高速串行差分接口（HSDI）设计实例,用QUARTUS和利用FPGA实现LVDS的方法。-High-speed serial differential interfaces (HSDI) design example implementation using FPGA LVDS QUARTUS and use of the method.
DDS
- 这是一个dds产生方波、三角波、正弦波的代码。请用Quartus II打开-This is a dds produce square wave, triangle wave, sine wave code. Please open the Quartus II
iir_16
- 用QUARTUS软件实现一个16阶的IIR滤波器-QUARTUS software with a 16-order IIR filter
Crack_QII_10.1_Windows
- quartus 10.1破解文件 内部人员用-quartus 10.1 crack file with internal staff
quartus.ii.11.0-crack
- 这是最新版的quartus11.0的破解文件，怎么做我就不说了，里面说的很清楚，我已经尝试，保证能用！希望大家学习愉快！ 另外此破解只做内部测试交流，切勿用于商业用途，否则后果自负，请勿广泛传播。-This is the latest version of the quartus11.0 the crack file, how do I do not say, which made it very clear, I have tri
rs232
- 用quartus仿真rs232的接收发射波形-quartus rs232
quartus-II
- 用Quartus II实现答辩计时器设置，大致功能有时间显示，倒计时提醒，暂停键等。-Quartus II realized by the respondent timer settings, roughly the time display function, countdown reminder, the pause button and so on.