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能综合的YCrCb2RGB模块（verilog)_采用3级流水线
- 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
3_3流水线
- 流水线作业练习，A、B机器处理作业1～5所需要的时间分别是『。。。。』『。。。。』，一台机器一次只能处理一个作业，一个作业只能由一台机器完成，求A、B完成所有作业的最短时间。-pipeline workbook, A, B machines handling a ~ 5 respectively, the time required is . . . . ]. . . . And one machine can handle only
流水线作业调度
- 按动态规划原理球解一类特定条件下的流水线调度问题的具体做法-according to the principles of dynamic programming ball a particular type of solution under the conditions of the pipeline scheduling problems, the specific way
三维流水线
- 三维流水线的功能-functional 3D Pipeline
MIPS五级流水线模拟程序
- MIPS五级流水线模拟程序，能执行简单的MIPS指令，模拟流水线状态及寄存器结果，实现cpu流水的概念-MIPS five-level stream-line simulation program, this program can execute simple MIPS instruction, simulat stream-line s status and register result, and it implements st
流水线调度
实现流水线调度
plc产品在流水线上的测试与分检控制
- 基于plc产品在流水线上的测试与分检控制.mwp
流水线CPU
- 流水线CPU的设计流程
靳远－源程序
- 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
GetCPU
- 一个利用DLL实现获得CPU信息的代码，十分专业，不但可以获得CPU的速度、型号等，而且可以获得CPU的缓存大小、流水线数等等30多项CPU的特性，而且，带了DLL的VC源程序-a DLL using information obtained CPU code, very professional, not only can the CPU speed, models, but the available CPU cache size,
三维流水线
- 三维流水线的功能-functional 3D Pipeline
pipe
- verilog编写的流水线模块-Verilog modules prepared by the Pipeline
MIPS
- 《MIPS五级整数流水线模拟系统》设计文档与源代码。 [代码性质] VC完整应用程序代码-The source and design document of <MIPS simulant system of 5 level int pipelining>. [code kind] VC whole application source code.
MIPS五级流水线模拟程序
- MIPS五级流水线模拟程序，能执行简单的MIPS指令，模拟流水线状态及寄存器结果，实现cpu流水的概念-MIPS five-level stream-line simulation program, this program can execute simple MIPS instruction, simulat stream-line s status and register result, and it implements st
Pipeline模拟
- 计算机体系结构中关于通用5级流水线的模拟实现程序-computer architecture on the common five Pipeline Simulation procedures
能综合的YCrCb2RGB模块（verilog)_采用3级流水线
- 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
流水线作业调度
- 按动态规划原理球解一类特定条件下的流水线调度问题的具体做法-according to the principles of dynamic programming ball a particular type of solution under the conditions of the pipeline scheduling problems, the specific way
微机控制的饮料包装流水线
- 某饮料包装流水线，一个包装箱能装12瓶饮料，要求每通过12瓶流水线暂停5秒，等待封箱打包完毕，然后重新启动流水线继续装箱。设计饮料包装流水线的控制电路，要求具有产量统计功能（数量及每箱生产时的时间-年月日小时分），发光二极管显示流水线的状态（运行、故障、打包）。(A beverage packaging line, a packing box can hold 12 bottles of beverages, requiring 12
滚筒流水线
- FX3U控制程序，带伺服及滚筒流水线，电网使用堆垛程序(FX3U control program, with servo and drum assembly line, the use of stack grid procedures)
流水线乘法累加器设计
- 调用寄存器LPM,流水线加法器LPM,流水线乘法器LPM等模块实现一个8位流水线乘法累加器。(Call a register LPM, pipelined adder LPM, pipeline multiplier LPM and other modules to achieve a 8 bit pipelined multiplication accumulator.)