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gcd
- 欧几里得算法求最大公约数电路的Verilog实现，消耗功率较低-Euclid algorithm for the realization of the common denominator Verilog circuit, lower power consumption
gcd
- 这是一个求最大公约数的verilog源码-this is a verilog source code which can count the greatest common divider .
verilog
- Verilog HDL 1.红外线发射调制电路 2.分数分频 3.最大公约数和最小公倍数 4.秒表-1.infra transmission modulator 2.fractal frequency divider 3.maximal common divisor 4.timer
Verilog
- 用verilog实现七位最大公约数的算法，使用状态机，可仿真电路图-Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation
GCD
- Verilog 最大公约数设计RTL级代码和芯片设计图-Verilog GCD Design and synthesis layout
gcd3
- 用verilog代码编写的GCD即找两个数之间的最大公约数的FPGA工程。-Verilog code written with the GCD of two numbers that find the common denominator between the FPGA project.
GCD_Verilog
- 利用Verilog语言写的采用更相减运算的球两个数的最大公约数-Using Verilog language written using a subtraction ball number two of the greatest common divisor
src
- 自己写的一个求两个32位操作数的最大公约数处理器的verilog代码，采用的是流水线结构-A seek the greatest common divisor of two 32-bit operands processor verilog code pipeline structure
mod.verilog
- 计算两个数值间的最大公约数和最小公倍数。-calculate two numbers greatest common divisor and lowest common multiple.
ee201L_GCD
- 用verilog代码编写程序求取两个数的最大公约数。-Verilog code with the preparation of procedures for the greatest common divisor of two numbers.
lowpower
- 最大公约数（GCD）stein算法实现，低功耗状态机实现(The greatest common divisor (GCD) stein algorithm, low power state machine implementation)
highperformance
- 最大公约数（GCD）stein算法实现，高性能流水线实现(The greatest common divisor (GCD) stein algorithm, high performance pipeline implementation.)
FPGA9 keyboard1
- 按键输入四位数，长按功能键排序或者求最大公约数并显示在数码管上(Key input four digit, press function key sequence or for the common denominator and digital tube display)
GCD
- 输入为两个32位数值，用辗转相减法实现的最大公约数算法进行输出，含有置位信号。(The input is two 32 bit values, and the algorithm of the greatest common divisor realized by the subtractive subtraction algorithm carries out the output, which contains the set si