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基于FPGA的数字秒表的VHDL设计
- 基于FPGA的数字秒表的VHDL设计
数字秒表课程设计
- 秒表程序课程设计，可以让那些不想写设计报告的人直接使用-stopwatch curriculum design process, allowing those who do not want to write the design report directly use
gaojingdushuzimiaobiao
- 高精度数字秒表，在pc机上用汇编语言模拟普通数字秒表，实现计时，暂停，继续，存储等功能。-high-precision digital stopwatch, the PCs used assembly language simulation ordinary digital stopwatch, time to achieve, suspended, continued, storage.
ghdfghhjetet
- 汇编语言实现的数字秒表 汇编语言实现的数字秒表-language compilation of figures compiled language stopwatch figures stopwatch
EDA_miaobiao
- 《数字电路EDA入门－VHDL程序实例》---数字秒表程序例子-"digital circuit EDA portal-VHDL program examples"-- digital stopwatch procedures example
byvhdstopwatchl
- 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital s
VHDLEXAMPLEppt
- 介绍8位加法器、分频电路、数字秒表的PPT，带源码，解释详细，一步一步学习，是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learnin
shuzimiaobiao
- 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
VHDL
- VHD设计实例8位加法器的设计分频电路数字秒表的设计-VHD Design 8 adder design of sub-frequency circuit design of digital stopwatch
Clock
- 用于体育比赛的数字秒表，计时器能显示 0.01ｓ的时间，最长计时时间为 24ｈ。-The number of sports competitions for the stopwatch timer can display the time 0.01s, the longest time to time 24h.
shuzimiaobiao
- 数字秒表的整个设计以及程序．波形仿真都在里面的了-Digital stopwatch, as well as the entire design process. Waveform simulation are inside the
suzimiaobiao
- 这个数字秒表写的很清楚，大家如果需要我还有一些资料！~-This figure clearly written stopwatch, U.S. If you need some information I have! ~
miaobiao
- 数字秒表，有分，秒，毫秒，精确度极高。使用verilong语言，程序短小精炼，非常值得参考。-Digital stopwatch, who, seconds, milliseconds, a very high accuracy. Verilong language used, procedures short refining, very worth considering.
kevin_timer
- FPGA 上的数字秒表及完整的显示功能。-FPGA digital stopwatch and complete display.
944
- 这是一个用汇编做的数字秒表!!这是一个用汇编做的数字秒表-This is a compilation make use of digital stopwatch!! This is a compilation make use of digital stopwatch
wtut_ver
- verilog HDL语言编写的数字秒表，仿真已经通过，可供参考-verilog HDL language digital stopwatch, simulation has already been adopted, for reference
shuzimiaobiao
- 数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through th
run_watch
- 提供一个数字秒表的EDA设计实例，内故有VHDL源代码，并有运行仿真图。-To provide a digital stopwatch the EDA design example, it is within the VHDL source code, and run the simulation of Fig.
digitalStopwatch
- 数字秒表的设计，设计并调试一个计时范围为0.01秒~1小时的数字秒表，并用实验开发系统进行硬件验证。有详细步骤和源码。-The digital stopwatch s design, designs and debugs a time scope is 0.01 second ~1 hour digital stopwatch, and carries on the hardware confirmation with the expe
Seconds
- 使用Keil开发的数字秒表，四位LED显示，具有暂停，清零功能，单片机课程设计。内附单片机原理图，程序注释详细，本人亲写。-Keil development using digital stopwatch, four LED display, with the suspension, Clear function, single-chip design courses. Containing a single-chip schemati