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verilog数字时钟论文及代码
- verilog数字时钟论文及源代码
数字频率计实验报告
- 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achie
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Develo
clock
- 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!-Written using Verilog HDL Digital Clock, has been verified in the development of on-board absolute originality, the use of digital tube display!
LED
- 数字时钟显示模块,用VERILOG HDL 实现-Digital clock display module, using the realization of VERILOG HDL
clock
- 本实验实现一个能显示小时，分钟，秒的数字时钟（贝一特电子）Verilog源码-The experimental realization of a can show hours, minutes, seconds, digital clock (a special e-bay) Verilog source
verilog
- 多功能数字时钟的verilog语言描述，基于quarters II平台-Multifunction digital clock verilog language descr iption of quarters II-based platforms
shuzishizhong
- 用verilog语言写的数字时钟程序 芯片是EP2C8Q208C8-Verilog language used to write the digital clock program chip EP2C8Q208C8
clock
- 基于fapa应用verilog语言实现多功能数字时钟-Verilog language based fapa application multifunction digital clock
verilog
- verilog语言编写的数字时钟程序，有计时，校准等功能-verilog language digital clock program
Verilog
- 用Verilog语言编写的多功能数字钟，用七段显示时钟-Verilog language, multi-function digital clock clock, seven-segment display
shuzishizhong-verilog
- 基于2410开发板数字时钟的开发，实现了计时，日期，跑表的功能-Based on the development of the 2410 development board digital clock, a time, date, stopwatch function
clock
- 一个简单的数字时钟Verilog仿真程序，60秒1分钟，60分一小时，24小时一天，265天一年。代码逻辑简化不含状态机，易理解。附激励文件可直接仿真。-A simple digital clock Verilog simulation program 60 seconds, 1 minute, 60 hours, 24 hours a day, 265 days a year. The code logic simplifies ex
FPGA-verilog-digital-clock
- FPGAverilog数字时钟,基于quartal ii 下的数字时钟电路程序-FPGA verilog digital clock
kcsj
- 利用Verilog层次化设计的多功能数字时钟，可以调时，设置闹钟，仿广播台整点报时(The use of Verilog hierarchical design of multi-functional digital clock, you can set the alarm clock, similar to the broadcast station, the whole point of time)
Digital_Clock
- 用verilog写的数字时钟代码，亲测可用，可自行编写test bench进行仿真(Written in Verilog digital clock code, pro test available, you can write your own test bench for simulation)
clock_shiyan
- 数电课程设计，数字时钟，基于Quartus II设计(Digital electric course design, digital clock)
digitial_clk
- 使用Verilog写时分秒数字时钟,实现基本的时钟计时功能。(Use Verilog to write time-division-second digital clocks for basic clocking.)
A4_Clock_Top1
- 描述了一个数字时钟，同时通过按键调整时间(descr iption of a digital clock, at the same time adjustment of time by keys)
FPGA_实时时钟设计
- 通过配置DS1302芯片来实现实时时钟的监测，我们通过通过控制2个按键来选择我们要在数码管上显示的时间，按下按键1我们来显示周几，按下按键2来显示年月日，不按显示时分秒，这样显示复合我们的数字表的显示(By configuring DS1302 chip to monitor the real-time clock, we select the time that we want to display on the digital tu