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并串转换XILINX
- 嵌入式中实现并串转换的VERILOG程序+VHDL程序两个版本，是xilinx版本的，权威但繁琐
s_pandp_s
- 用VHDL编写的并串转换和串并转换实例，希望对您有所帮助，其中输入数据是时钟的16倍-prepared using VHDL and string conversion and string conversion and examples, and I hope to help you, the input data which is 16 times the clock
IIS2BT656
- 本程序功能为将音频的IIS数据插入bt656数据中一起传输。在程序中，sdata并不从外界输入，而是由内部的一个16位的counter并串转换产生，以此来检测程序在串并转换sdata时是否有遗漏。 本程序并未经过实测，但ModelSim的仿真结果正确。-this program will function as audio data into IIS bt656 together data transmission. In the
SPI-PRT
- 昨天在论坛上看到有人帖出了他写的并串转换VHDL代码，但是他自己说有问题，但是不知道怎么改。我大概看了一下，发现思路还是比较乱的。于是就写下了我自己的并串转换代码。-yesterday at the forum see someone points out his writing and string conversion VHDL code, But he said there are problems, but does not k
xapp514_hd-integ-demobrd
- SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写-SDI interface of the source, including interference coding and string conversion, using VHDL hardware descr iption language
p2s16_1
- 前段时间看见有人在网上求并串转换的程序，今天闲了，就编了一个供大家参考一下。 其实是很简单的，只要理清思路，还是很容易的 。-Some time ago to see someone in the online order and string conversion procedures, idle today, and on the allocation of a reference for everyone. In fact,
sditest
- 基于ep3c25的altera sdi ip核的使用，串并转换和并串转换-Ep3c25 based on the altera sdi ip nuclear use, and conversion and string and string conversion
bc_6
- 实现6位数据宽度的并串转换，编译和仿真完美实现,编程环境Quartus.
1253
- 基于VHDL语言的并串转换程序，有四位的并行输出转换为串行输出-Based on the VHDL language and string conversion process, there are four parallel output is converted to serial output
chuan2
- 用verilog HDL编写的并串转换模块，在ISE软件仿真过，也可综合-Prepared using verilog HDL and string conversion module, in the ISE software simulation, and can also be integrated
bingchuan2
- verilogHDL编写的并串转换模块，在ISE软件中仿真过，可综合，绝对是正确的-prepared and verilogHDL string conversion module, the ISE simulation software that can be integrated, is absolutely correct
bingchuan
- verilogHDL编写的并串转换模块，在ISE软件中仿真过，可综合，绝对是正确的-prepared and verilogHDL string conversion module, the ISE simulation software that can be integrated, is absolutely correct
p2s
- 并串转换器：将并行输入的信号以串行方式输出，这里要注意需先对时钟进行分频，用得到的低频信号控制时序，有利于观察结果（可以通过L灯观察结果）-And series converter: the input signal in parallel to serial output, where attention should be paid to the need to carry out first clock frequency, lo
p2s
- 并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。-And the string conversion module, which contains another one. Vhd file. One is its relatively simple to write the other is the reference.
signal_output
- 本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight
serial_input_parallel_output_module
- 有一批数据并行输入，位宽为4，输入的时钟频率是20MHz，模块的功能是对这些数据进行并串转换。它每收满6个数据（一个包），就对这6个数据进行处理，将这6个数据按照一定的顺序串行输出，输出的时钟频率是80MHz-serial input parallel output
74HC165
- 8051系列单片机控制74HC165并串转换-c51程序-8051 Series MCU control 74HC165 and string conversion-c51 program
ser_par
- 24bitAD数据采样进行串并转换，并行输出。另包括24位DA并串转换，串行输出。-24bitAD data sampling and converted to strings, parallel output. Other notable features include 24-bit DA and string conversion, serial output.
p_s
- 用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中-VHDL language with the realization of an 8-bit data, and the string conversion, can be downloaded in the FPGA in
s_p
- 用Verilog HDL语言进行并串转换，并通过Quartus Ⅱ 功能仿真验证-With the Verilog HDL language and string conversion functions through simulation Quartus Ⅱ