搜索资源列表
at89c52_DS1302
- AT89C52实时时钟DS1302测试,带Proteus文件，可软件仿真运行。-AT89C52 Real Time Clock DS1302 tests with Proteus documents, Simulation software can be run.
verilog_multiplier
- verilog实现16*16位乘法器，带测试文件-verilog achieve 16 * 16 multiplier, with test documents
shiftreg
- verilog实现shiftreg，带测试文件。 文件相當完整，可以下載去測試
verilog_multiplier
- verilog实现16*16位乘法器，带测试文件-verilog achieve 16* 16 multiplier, with test documents
shiftreg
- verilog实现shiftreg，带测试文件。 文件相當完整，可以下載去測試-Verilog realization shiftreg, with the test document. Document rather complete, and can be downloaded to test the
pn_generator
- FPGA实现pn发生器，Verilog代码实现，另带modlesim的仿真测试文件，很有价值。-FPGA realization of pn generator, Verilog code, and the other with the simulation test modlesim documents of great value.
cmmb_MFS_sample
- 手机电视行业标准CMMB的码流MFS分析软件并带测试文件*.MFS，对手机电视学习者有帮助哦-CMMB MFS TEST SOFTWARE AND TEST FILE
ps2
- ps/2键盘驱动器程序键盘VHDL编写，带测试文件-ps/2 keyboard driver code ,program with VHDL,with test file
ASK_modulator
- 振幅键控ASK的调制解调Verilog实现，带测试文件-ASK amplitude shift keying modulation and demodulation Verilog implementation, with the test file
FSK
- 频移键控FSK的Verilog实现，带测试文件，并在FPGA开发板上成功验证-Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board
prbs
- 伪随机二进制序列发生器的Verilog源码，带测试文件，并在FPGA开发板上成功验证-Pseudo-random binary sequence generator Verilog source code, with a test file, and successfully verified in FPGA development board
clock_norst
- 时钟显示，verilog 代码，时钟实现没有使用复位信号，带测试文件-Clock display, verilog code, the clock to achieve without the use of a reset signal, with the test file
DDS
- verilogHDL语言编写，带测试文件DDS波形发生器.-DDS waveform generator, verilogHDL language, with the test file
G711_codec_file.tar
- G711 codec ,内带测试文件,对学习G711有很大帮助-G711 codec, with a test file of great help in learning G711
uart_verilog
- 串口标准通讯，带奇偶校验和通讯超时故障，带测试文件-The serial standard communication with test files
Kalman-matlab
- 传感器姿态解算 matlab工具箱全部程序自带测试文件程序-Sensor attitude algorithm matlab toolbox full program comes with the test documentation procedures
buttons
- 基于xilinx zynq平台下的linux系统中的按键测试程序,带makefile文件(Xilinx zynq platform based on the Linux system button test procedures, with makefile files)
FileIO
- 一个简单的带buffer的文件I/O 类。实现了简单的 缓写 和 预读 策略，代码有注释，本代码仅供演示参考请勿用于实际项目。(入口文件的代码是用于测试文件合并的例子)(A simple I/O file class with buffer. The slow and write simple Prefetching Strategy, annotated code, the code is for reference for act
8-8DCT变换verilogHDL代码
- DCT变换实现图像压缩及嵌入水印等,内含测试文件及DCT算法讲解(Image compression and embedding watermark by DCT transform)
j1699-ver-16.04.00
- 国六型式核准测试国际标准源代码，带项目文件，可以在Visual Studio中直接加载编译生成DOS文件。(J1699-3 Compliance Test Source Codes)