搜索资源列表
multi_cpu
- 多周期CPU，mips指令集，实现了部分指令，包含测试程序，verilog-Multi-cycle CPU
multi_cpu
- 使用Verilog语言编写的多周期CPU,能实现CPU24条指令，-Using the Verilog language multi-cycle CPU, can achieve CPU24 instructions,
CPUdesign
- 计算机组成原理实验多时钟周期CPU设计，包含VHDL代码的设计，实验电路图，实验详细截图。-Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.
MultiCLKCPU
- 本设计实现了多周期CPU的设计，运行环境是quatrus2；该多周期CPU可以处理22条32位指令（具体指令见源码，绝不坑人）。压缩包内含有源代码，程序模块表和实验报告以及详细的设计图，是学习verilog的好材料啊。-The Design and Implementation of a multi-cycle CPU design, operating environment is quatrus2 the multi-cycle
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
CPU
- 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
MulticlockCPU.tar
- verilog hdl实现多周期CPU，按照有限状态己设计，含源码、实验报告和详细vsd电路图-verilog hdl multi-cycle CPU, in accordance with the finite-state has been the design, including source code, test reports and detailed schematic vsd
CPU
- 用硬件编辑语言，实现一个多周期cpu 的内核部分。-Editing language in hardware to achieve a multi-cpu core part of the cycle.
CPU-source-code
- CPU设计代码，包括单周期CPU，多周期CPU，流水线CPU及相关ALU组件。-CPU design code, including single-cycle CPU, multi-cycle CPU, ALU pipeline CPU and related components.
CPU
- 多周期cpu结构有特点，性能优良，便于理解。-This cpu is very good.It is easy to understand.
mips--cpu
- 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU
multi-CPU
- Verilog开发的能下载到FPGA实验板上运行的多周期CPU-Verilog can be downloaded to the FPGA development board running experiments multi-cycle CPU
cpu-7-verilog
- 多周期cpu设计asadsdddasd-multi cpu design
CPU
- 多周期CUP用MIPS汇编的实现，包含了测试指令。(Multi cycle CUP with MIPS compilation of the implementation, including the test instructions.)
mul_cycle_cpu_1
- 多周期CPU设计详细代码及在ISE下面的仿真(Multi cycle CPU design detailed code and simulation)
MCPU
- 多周期CPU的verilog代码，用vivado可以仿真出波形(multi-cycle CPU by verilog and using vivado to simulate.)
前导零CPU
- 在多周期CPU的基础上设计一个前导0检测程序。(A preamble 0 detection program is designed on the basis of multi period CPU.)
Multi_cpu
- 多周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
mCPU
- 多周期CPU, 可参考程序, 详情请结合网上的实驗报告(Multi cycle CPU, reference program. For details, please combine the experimental report on the Internet)
2017级计算机组成原理课程设计任务1--CPU设计实验
- 学习计算机组成原理的必备利器 用实际操作来亲身感受计算机的内部工作原理(A necessary tool for learning the principle of computer composition Experience the inner workings of a computer with actual operation)