搜索资源列表
8BIT
- 基于FPGA的8位乘法器代码,可以进行四象限乘法
shiweichenfaqi
- maxplus做的四位乘法器，可下载仿真
applicationofhardwaredescripptionlanguageCVHDLinth
- 通过四位乘法器的实例详细介绍了用ＶＨＤＬ语言设计数字系统的流程和方法，通过仿真实现预定目的．
multi_vhdl
- 四位乘法器的VHDL源程序-four Multiplier VHDL source
multi_vhdl
- 四位乘法器的VHDL源程序-four Multiplier VHDL source
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Develo
multi4
- fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier
8BIT
- 基于FPGA的8位乘法器代码,可以进行四象限乘法-FPGA-based 8-bit multiplier code, can be four-quadrant multiplication
shiweichenfaqi
- maxplus做的四位乘法器，可下载仿真-The four maxplus multiplier, can be downloaded Simulation
applicationofhardwaredescripptionlanguageCVHDLinth
- 通过四位乘法器的实例详细介绍了用ＶＨＤＬ语言设计数字系统的流程和方法，通过仿真实现预定目的．-Through the four examples of multipliers detailed design using VHDL language digital system processes and methods, through the simulation to achieve the intended purpose.
chengfaqi4
- 用VHDL实现四位乘法器，不直接用乘法实现，一来节省资源，二来可提高速度！-Use VHDL to achieve four multiplier, not the realization of the direct use of multiplication, one to save resources, and secondly to improve the speed!
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binar
mux4
- 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic descr iption of
chengfa
- 可编程器件已有很久的发展历史了，其功能之卓越和成熟已经令当今的电子工程师们赞叹不已，除了它体积小、容量大、I/O口丰富、易编程和加密等优点外，更突出的特点是其芯片的在系统可编程技术。四位乘法器程序,VHDL语言,仿真图形 开发-four process
4_bit_mul
- 四位乘法器,可以实现两个四位二进制数的乘法。-4_bit_mul
four-bit-mul
- 用加法器乘法树实现四位乘法器。绝对可以实现，大家不妨下来-Achieved with the four adder tree multiplier multiplication
Four-multipliers-with-VHDL-
- 用VHDL实现四位乘法器，不直接用乘法实现。该代码思路清晰，希望可以帮助到大家！-Four multipliers with VHDL implementation, not directly with the multiplication implementation. The code is clear thinking, I hope to help to you!
4BITMULT
- 基于FPGA的四位乘法器，在QuartusII上编译通过可实现，采用VHDL语言编写。-Based on FPGA four on time-multiplier, in QuartusII compiled can be realized through, the VHDL language.
multi_4
- 自己用写的VHDL的四位乘法器，实现方式比较简单-Write the VHDL four multipliers to achieve relatively simple way
EDA
- EDA课程设计，设计的四位乘法器，原理，仿真结果及其原程序。-EDA curriculum design, the design of the four multipliers, the principle of simulation results and its original program.