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分频器FENPIN1
- EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time - with a counter by the external input is required when the sub-frequency
5分频、移相VHDL程序
- 有两端VHDL程序，5分频的和分频移相的，希望大家用的上
fpq128
- 自己编的一个分频器的程序模版 虽然原理很简单，经过多次实践很实用 被多次用在其它的程序中-own series of the dividers of a procedure template Although very simple principle, after repeated practice by many very practical use in other proceedings, and,
分频器FENPIN1
- EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency
32fenpinqi
- 这是用VHDL语言写的32位分频器的程序，可直接运行，看结果，欢迎使用。多指正，交流。-This is written in VHDL 32 dividers procedures can be run directly see the results, welcomed the use. More correct exchange.
beipin
- 用verilog写的cpld的各种分频程序，希望大家指正，谢谢！-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
fenpin
- 本程序是用VHDL语言，非整数分频的一个实现， fenpin.vhd为主程序-this procedure is used VHDL, non-integer frequency of a realization of the main procedures fenpin.vhd
sanfenpin
- 这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可-This was my third prepared by the frequency, which is odd hours, frequency and duty ratio of 1:1. Of course, if the needs of other odd hours, frequency, as l
shifter_for_xiaojiexu
- 可以实现IO口在微处理器上的扩展，集成了分频，移位等技术，是个很不错的程序-IO mouth can be achieved in the expansion of microprocessors and integrated sub-frequency, displacement, and other technologies is a very good procedure.
half_clk
- 用verilog编写适中分频器 并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
fdivision
- 用verilog编写适中分频器 并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
FPGA_fenpin
- 分频器 FPGＡ程序设计 二分频 对硬件设计有很大用处 -Divider FPGA design process for two minutes frequency hardware design, very useful
S4_FENGPING
- 这是一个用VHDL语言写的分频程序,可用得着-This is a VHDL language used to write the sub-frequency procedures, can be useful
three_division_VHDL_programe
- 根据上面思想写的三分频程序,1/3和50％占空比的程序.-According to the above one-third the frequency of thinking of writing procedures, 1/3 and 50 duty cycle procedures.
miaobiao
- verilog写的分频程序,可以对输入的频率分频-Verilog write the sub-frequency procedures, can the frequency of the input frequency
f50k
- VHDL产生时钟50分频程序，供初学者参考-VHDL generated clock frequency of 50 procedures, the reference for beginners
integerdivider
- 一个任意整数分频程序,采用VHDL语言编写，编译通过-An arbitrary integer frequency procedure for the VHDL language, the compiler through
divide
- 关于verilog的分频程序 等占空比 非等占空比 小数分频 奇数分频-Verilog frequency on the sub-procedures such as the duty cycle of non-duty-cycle fractional odd frequency, etc.
fenpin
- 利用vhdl写的分频程序，芯片是LATTICE的(Using VHDL to write frequency division procedures, the chip is LATTICE)
fp
- 通过quartus2软件使用VHDL语言将输入频率分频的程序(divide the frequency)