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sub_full_n
- 该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.
sub20
- 一个减法器的程序,经过调试的,还是非常好用的.-A subtraction device procedure, after debugging, still very useful.
add_sub_lab2
- 实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl descr iption, including analysis and reporting.
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Develo
verlog_basic
- 用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器，乘法器，除法器，多路选择器，二进制转BCD码，加法器，减法器等等。-verlog used some language addendum to the basic experiment, which is suitable for FPGA/CPLD beginners. Including eight priority encoder, mu
vhdlsource
- 用verilog hdl编写的一些例程，包括加法器/减法器等等，例子较多就不一一列举了-Verilog hdl prepared with some routines, including the adder/subtraction, etc., for example, more is not to enumerate the
seg47
- 一个数码管显示的测试程序，内含加法器、减法器，4-7译码器，计数器等。-A digital display of test procedures, including an adder, subtraction device ,4-7 decoder, counters and so on.
8_jjfq
- 用VHADL和Verilog HDL实现带进位的8位加减法器。-Using Verilog HDL and realize VHADL into 8-bit instruments used in addition and subtraction.
VHDLjianfaqi
- 这是一个利用MAX PULL 制作的VHDL的减法器的程序 如果有需要仿真图的 请叫站长联系我-This is a MAX PULL produced using VHDL s process of subtraction, if necessary simulation diagram contact me please call station
jianfaqi
- 用硬件描述语言编程实现减法器,实现两个操作数的减法-Using hardware descr iption language programming subtraction, and the achievement of the two operands of the subtraction
OPERATION_UNIT
- 本程序为加密芯片内部加密运算单元部分，包括32位减法器、移位寄存器、加/减法器、寄存器等，对密码芯片运算部分设计具有一定指导意义-The procedure for encryption chip unit internal encryption algorithms, including 32-bit subtraction, and shift register, add/subtraction, and register and
Mars_EP1C6F_Fundermental_demo(Verilog)
- FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and m
as
- 自己编写的的，基于verilog的加减法器！！！比较简单-Their written, based on instruments used in verilog addition and subtraction! ! ! Is relatively simple! !
jiajianfaqi
- 利用VHDL语言设计的两位加减法器，设计采用BLOCK并行设计可以同时进行加法与减法运算-VHDL language design using addition and subtraction of two instruments used, designed using BLOCK parallel design can be done concurrently addition and subtraction
VHDL
- 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
jian
- 一个简单的减法器，适合初学者，高手就不用看了-A simple subtraction, for beginners, masters do not need to read
jiafqi
- vhdl减法器 用vhdl语言实现减法功能-Used subtraction vhdl vhdl language subtraction function
ADD_SUB_32bit
- 加减法器，可实现有无符号数的加减法-Modified instruments used, can be realized whether the number of addition and subtraction symbols
FPGAVerilogHDLcode.RAR
- 一些例程供参考，包括加法器，减法器，多路选择器-failed to translate
Verilog
- 32位存储器Verilog附带test文件，可以在modulesim仿真 还有加法、减法器，译码器等常用Verilog器件，都附带仿真test。-Memory test with Verilog