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变采样率全数字相位载波解调技术
- 基于相位载波( PGC , Phase Generated Carrier) 解调各环节的信号频率范围，提出变采样率解调方案，解决高采样频率下的实时全数字PGC 解调问题.
verilog全数字锁相环pll
- verilog全数字锁相环，用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
全数字锁相环
- 详细介绍数字锁相环的工程
verilogpll
- 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
010919.pdf
- 全数字锁相环ＶＨＤＬ描述并实现功能仿真，另附有图形说明-DPLL VHDL descr iption and achieve functional simulation, followed by graphic shows
pll_improvement
- 一种改进的全数字锁相环设计 一种改进的全数字锁相环设计-an improved DPLL design an improved design DPLL
verilogpll1234
- 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
060107[1].pdf
- 全数字锁相环,包括ＤＰＤ，ＤＬＦ，ＤＣＯ．-DPLL, including the DPD, DLF, the making.
testbench
- 一个自己编写的全数字锁相环及其测试向量，比较简单但功能基本达到。-I have written an all-digital phase-locked loop and its test vectors, relatively simple to achieve but the basic function.
clkrecoveryDPLL
- 用于时钟恢复的全数字锁相环设计，可以去掉时钟的抖动。-Clock recovery for all-digital phase-locked loop design, the clock jitter can be removed.
Matlab_model
- 在MATLAB环境下，对全数字锁相环的仿真，分析锁相环的性能参数-In the MATLAB environment, to all-digital phase-locked loop simulation, analysis of the performance parameters of phase-locked loop
DPLL2
- 全数字锁相环电路的研制，使用的是VHDL语言 -All-digital phase-locked loop circuit development, using the VHDL language
FPGA444555443
- 基于FPGA的全数字锁相环设计,内有设计过程和设计思想-FPGA-based all-digital phase-locked loop design, with the design process and design thinking
ADPLL
- 全数字锁相环（adpll)的部分源程序代码，是其中最重要的部分。-All-digital phase-locked loop (adpll) part of the source code, is one of the most important part.
pll_verilog
- 全数字锁相环的verilog源代码,仿真已通过 -All-Digital Phase-Locked Loop verilog source code, simulation has passed
2009
- 智能全数字锁相环的设计,基于FPGA实现。-Intelligent all-digital phase-locked loop design, FPGA-based implementation.
verilog
- 采用用verilog语言编写的全数字锁相环的源代码。-Verilog language used by all-digital phase-locked loop' s source code.
VHDLDPLL
- 基于VHDL 的全数字锁相环的设计，里面包含了最核心的程序。-VHDL-based all-digital phase-locked loop design, which contains the core procedures.
DPLL
- 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug