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用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
基于半加器的全加器描述及仿真
- vhdl基于半加器的全加器描述及仿真-VHDL-based increases for the entire increase Descr iption and Simulation
8bit全加器带进位复位功能
- 8bit全加器带进位复位功能 已经通过防真
4位全加器
- 基于matlab的4位全加器，能正常运行。
4位全加器
- 基于matlab的4位全加器，已通过运行。
4位全加器
- 4位全加器
基于半加器的全加器描述及仿真
- vhdl基于半加器的全加器描述及仿真-VHDL-based increases for the entire increase Descr iption and Simulation
VHDL大作业－虞益挺036100486
- 全加器的VHDL程序实现及仿真-full adder VHDL simulation program and
用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
full_add
- 一个用VHDL语言编写的8位全加器，并且扩展了减法功能，带有状态位的判断。-a VHDL prepared by the eight-adder, and extends the subtraction function, with state-of judgment.
Full_Adder
- 全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼-full adder and the VHDL_CODE TEST_BENCH not extract passwords
5-2-2ModelSim
- MODELSIM 环境下的Verilog 源代码，实现全加器功能-MODELSIM environment Verilog source code, the entire increase functionality
add_sub_lab2
- 实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl descr iption, including analysis and reporting.
jiafaqi
- 实现四位加法器的VHDL代码，里面含有全加器的代码-achieve four Adder VHDL code, which contains the full adder code
multi4
- fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier
4bitadd
- 4位全加器原码，包括仿真码和4位计数器码。-four full adder original code, including the simulation code and four counter code.
10vhdlexamples
- 10个VHDL程序实例，包括加法器，全加器、函数发生器，选择器等。-10 examples of VHDL procedures, including the adder, full adder, function generator, selector and so on.
myproject
- 四位全加器，VHDL语言，max+plusII平台做的-Four full-adder, VHDL language, max+ PlusII platform to do
VHDL
- 自编自写的ＶＨＤＬ代码，用于实现全加器功能，可能有误-, Directed and written in VHDL code, for the realization of full-adder function, may have mistaken
1位加法器
- 一位全加器的功能，原理图，代码，还有一些基本使用的应用，让一位全加器能正常运行。(Function and application of a full adder)