搜索资源列表
vhdl
- 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。
vhdl
- 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。 -Pseudo-random sequence generator algorithm VHDL design of a pseudo-random sequence generator, using the generation polynomi
M
- 基于51单片机实现的M序列发生器（伪随机序列），在Keil编程环境下的源码-Based on 51 single-chip realization of M sequence generator (pseudo-random sequence), in Keil of-source programming environment
m_vhdl
- 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）-m sequence vhdl
VHDL
- 8*8乘法器设计 伪随机序列发生器 PS2键盘设计 均为VHDL-8* 8 multiplier design of pseudo-random sequence generator are PS2 keyboard design VHDL
CPLD-radom
- 基于C P L D 的伪随机序列发生器，用FPGA产生随机序列的-CPLD-based pseudo-random sequence generator, generate random sequences using FPGA
LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear fee
vhdl
- 伪随机序列发生器得VHDL语言源代码，已通过仿真。-Pseudo-random sequence generator may VHDL language source code, by simulation.
m_vhdl
- 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。-Design a pseudo-random sequence generator, using the generating polynomial 1+ X ^ 3+ X ^ 7. Requires a RESET terminal end and two control regist
random
- 产生符合一定分布的随机数的方法是，先产生(0，1)均匀分布的随机数，然后通过一个适当的变换方法得到所要求分布的随机数。常用的均匀分布伪随机序列发生器有线性同余发生器和线性反馈移位寄存器两种。-That meet certain distribution of the random number is first generated (0,1) uniformly distributed random number, then an ap
randHe
- 基于Henon映射的混沌伪随机序列发生器，用MATLAB7.1实现-Henon mapping based on Chaotic Pseudo-random sequence generator, to achieve with MATLAB7.1
LFSRRC4
- 伪随机数发生器LFSR RC4加密与解密 根据算法原理，首先初始化S-BOX，产生伪随机序列密钥流，选择所加密文件与密钥流异或生成密文 -Pseudo-random number generator LFSR RC4 algorithm for encryption and decryption based on the principle, first initialize the S-BOX, pseudo-random s
VHDL-source-code
- 一些有用的VHDL代码 包括伪随机序列发生器等-VHDL code, including some useful pseudo-random sequence generator, etc.
sequential-detactor
- 本次例程包括七阶伪随机序列发生器、序列码检测器，奇偶校验器、CRC（循环冗余）校验器，并附有FPGA的代码和仿真。-The routines including seven order pseudo-random sequence generator, sequence yards detector, parity validator, CRC (cyclic redundancy) validator, and with FPGA c
pseudo-random-sequence-generator-
- 利用FPGA编程--- -实现“伪随机序列发生器设计”-FPGA programming------- pseudo-random sequence generator design
seq_gen
- matlab编写的伪随机序列发生器，包括小m序列、大M序列，gold序列-pseudo-random sequence generator matlab prepared, including a small m sequence, M sequences, gold sequences
18472582m_sequence_3
- 基于lfsr的伪随机序列发生器，带有游程检测-Pseudo-random sequence generator based on lfsr with run detection
random
- 8位伪随机序列发生器。在通信加扰，序列检测中有很强的工程应用-8 pseudo-random sequence generator. In communications scrambling sequence detection has a strong engineering applications
pseudo8
- 8位伪随机序列发生器设计，可以进行时序仿真和功能仿真-The design of 8 bits Pseudo-Random Binary Sequence,you can do Timing simulation and function simulation
伪随机序列
- 如果一个序列，一方面它是可以预先确定的，并且是可以重复地生产和复制的；一方面它又具有某种随机序列的随机特性（即统计特性），我们便称这种序列为伪随机序列。(If a sequence is predefined on the one hand, it can be produced and replicated repeatedly; on the one hand, it has a random sequence of random