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CPLD任意分频输出 VHDL
- CPLD任意分频输出 VHDL,调试通过
任意分频代码(VHDL)
- 任意分频代码(VHDL)
clk_divide_3
- VHDL语言编写三分频，可以扩展实现任意奇数-VHDL prepared three frequency can be extended to achieve arbitrary odd
ClockOut
- 通过VERILOG编程，实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
clk_div
- 自己编写的任意分频VHDL程序，程序简单，以供大家分享！-prepare their arbitrary frequency VHDL procedure is simple and for all to share!
VHDLnf
- VHDL实现任意整数分频，--只要把n设置成你要分频的数值就可以了-VHDL arbitrary integer frequency,-- n as long as you want to set the frequency of the numerical breakdown on the
fenpin
- 任意数分频的各种设计方法，包括奇偶分频，小数分频等等。-Arbitrary number of sub-frequency of the various design methods, including the odd-even split frequency, fractional-N and so on.
fqdiv
- 能够实现0~99的任意分频,并实现输出频率50％的占空比-0 ~ 99 to realize the arbitrary frequency and to achieve an output frequency of 50 duty cycle
renyifenpin
- 任意分频的vhdl实现，若需要具体参数，只需改变程序中的分频参数即可实现。-Arbitrary frequency of VHDL realize that if the needs of specific parameters, simply change the process parameters of the sub-band can be realized.
ddddd
- 用以实现信号的任意分频，用于信号的精确分频-For the realization of arbitrary sub-frequency signals for precise signal frequency
Frequency_divider
- 用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
VHDL
- 实现任意小数分频的VHDL源代码，方便，快捷，提供丰富的资料可供参考，希望大家喜欢-Realize arbitrary fractional-N of the VHDL source code, convenient, provides a wealth of information for reference, I hope everyone likes
any_div_freq
- 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.-Can be arbitrary points on the input clock frequency (integer or decimal), with complete Quartus II project document.
bxfsq
- 用VHDL代码实现的0-40000任意分频,具体分频数可以自己参考进行修改.并用matlab写好各种波形图的MIF文件,然后实现FPGA的一个多功能波形生成器! (平时的课程设计)-Achieved using VHDL code 0-40000 arbitrary frequency, the specific sub-frequency reference can be modified. Matlab written by a v
ryfp
- 任意分频,可以自动生成Hdl代码，图形界面操作简单，功能独特-Arbitrary frequency can be automatically generated Hdl code, graphical interface is simple, unique features
div
- verilog任意分频电路实现，仿真效果非常好-div dclk
fenpinVHD
- 任意分频的VHDL 任意分频的VHDL-Any sub-band frequency VHDL any sub-sub-frequency VHDL arbitrary VHDL
clk_div_n
- 时钟任意分频模块，输入为主时钟和分频数，输出为主时钟/分频数。-Clock divider
N_Separate-frequency-device
- 可以输入0到2的5次方的任意分频的分频器-Separate frequency device
random frenquency division
- verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)