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verilog实现串并转换模块
- verilog实现串并转换模块
verilog实现串并转换
- verilog实现串并转换的源代码
verilog vhdl编写的串并转换
- verilog vhdl编写的串并转换
pn_code
- 系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b
u-uart
- 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
S2P_xapp194
- VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source
SPtransform
- Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
verilogzzhwfy
- 用Verilog实现QPSK中的差分,扰码,串并,解差分,解扰码,解串并,用MUXPLUS2进行仿真-QPSK with Verilog realize the difference, code, and serial, Xie difference, encryption codes, and solutions Series, The simulation used MUXPLUS2
bunchcombinechange
- Verilog源代码,实现串并转换，学Verilog的不错的基本例程-Verilog source code, realize SERDES, learning Verilog good basic routines
Verilog_serdes
- 用verilog写的串并转换程序,希望对大家有用!-Written using Verilog string and the conversion process, in the hope that useful to everybody!
chuanbing
- 自己编写的串并变换的fpga程序，使用verilog语言-I have written FPGA series and transform, the use of Verilog language
verilog
- verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
auk_sdsdi
- 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
s2p
- 一个串并转换的Verilog源码，有questasim仿真。-A string and convert the Verilog source code, there are questasim simulation.
32bitshiftregister
- 32位带锁存移位寄存器,采用verilog HDL语言编写，可用于串并转换-32-bit shift register with latches, using verilog HDL language can be used for string and convert
cbzh
- 串并转换的verilog文件带仿真结果图片的-String and convert the verilog file with simulation results pictures
SERDES
- 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion fun
verilog串口通信程序
- 串口通信程序，用于fpga的串口收发，并讲解了串口通信原理。(Serial communication program is used to receive and transmit the serial port of FPGA, and the principle of serial communication is explained.)
Verilog的135个经典设计实例
- Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码
uart_v1.1
- Quartus下开发Verilog编写的串口程序，主要包含串并互转模块等，通过RTL和时序仿真(Quartus under the environment of a serial procedures written in Verilog, contains the Conversion module and so on RTL and timing simulation has passed)