文件名称:sdram_control

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2017-12-07
  • 文件大小:
  • 2.7mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • Dean*****
  • 相关连接:
  • 下载说明:
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SDRAM控制器 带仿真模型文件  仿真通过(Simulation model file simulation through SDRAM controller)
相关搜索: SDRAM控制器

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
sdram_control\sdram_control\doc\read_me.doc 24576 2005-11-22
sdram_control\sdram_control\doc\SDRAM.doc 417280 2005-12-15
sdram_control\sdram_control\doc\sdr_sdram.pdf 917283 2002-09-02
sdram_control\sdram_control\sim\altera_mf.v 1139393 2004-11-28
sdram_control\sdram_control\sim\Command.v 17532 2005-06-18
sdram_control\sdram_control\sim\control_interface.v 8494 2004-11-28
sdram_control\sdram_control\sim\mt48lc2m32b2.v 50092 2004-09-03
sdram_control\sdram_control\sim\Params.v 935 2005-06-14
sdram_control\sdram_control\sim\sdram_test.cr.mti 4318 2005-12-17
sdram_control\sdram_control\sim\sdram_test.mpf 23380 2005-12-17
sdram_control\sdram_control\sim\sdram_test.wlf 57344 2005-11-22
sdram_control\sdram_control\sim\sdram_test_tb.v 7397 2005-12-17
sdram_control\sdram_control\sim\transcript 4605 2005-12-15
sdram_control\sdram_control\sim\vsim.wlf 57344 2005-12-17
sdram_control\sdram_control\sim\wave.do 2616 2005-12-17
sdram_control\sdram_control\sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm 28793 2005-12-17
sdram_control\sdram_control\sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat 2947 2005-12-17
sdram_control\sdram_control\sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.vhd 104 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_pll_reg\verilog.asm 4304 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_pll_reg\_primary.dat 478 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_pll_reg\_primary.vhd 354 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_ram7x20_syn\verilog.asm 26147 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_ram7x20_syn\_primary.dat 2141 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_ram7x20_syn\_primary.vhd 586 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_stratixii_pll\verilog.asm 596560 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_stratixii_pll\_primary.dat 52333 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_stratixii_pll\_primary.vhd 6750 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_stratix_pll\verilog.asm 753435 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_stratix_pll\_primary.dat 72503 2005-12-17
sdram_control\sdram_control\sim\work\@m@f_stratix_pll\_primary.vhd 8453 2005-12-17
sdram_control\sdram_control\sim\work\alt3pram\verilog.asm 147437 2005-12-17
sdram_control\sdram_control\sim\work\alt3pram\_primary.dat 10137 2005-12-17
sdram_control\sdram_control\sim\work\alt3pram\_primary.vhd 1938 2005-12-17
sdram_control\sdram_control\sim\work\altaccumulate\verilog.asm 53145 2005-12-17
sdram_control\sdram_control\sim\work\altaccumulate\_primary.dat 3891 2005-12-17
sdram_control\sdram_control\sim\work\altaccumulate\_primary.vhd 923 2005-12-17
sdram_control\sdram_control\sim\work\altcam\verilog.asm 600522 2005-12-17
sdram_control\sdram_control\sim\work\altcam\_primary.dat 47018 2005-12-17
sdram_control\sdram_control\sim\work\altcam\_primary.vhd 1731 2005-12-17
sdram_control\sdram_control\sim\work\altcdr_rx\verilog.asm 155436 2005-12-17
sdram_control\sdram_control\sim\work\altcdr_rx\_primary.dat 15220 2005-12-17
sdram_control\sdram_control\sim\work\altcdr_rx\_primary.vhd 1173 2005-12-17
sdram_control\sdram_control\sim\work\altcdr_tx\verilog.asm 140810 2005-12-17
sdram_control\sdram_control\sim\work\altcdr_tx\_primary.dat 12496 2005-12-17
sdram_control\sdram_control\sim\work\altcdr_tx\_primary.vhd 937 2005-12-17
sdram_control\sdram_control\sim\work\altclklock\verilog.asm 144800 2005-12-17
sdram_control\sdram_control\sim\work\altclklock\_primary.dat 14142 2005-12-17
sdram_control\sdram_control\sim\work\altclklock\_primary.vhd 1608 2005-12-17
sdram_control\sdram_control\sim\work\altddio_bidir\verilog.asm 13065 2005-12-17
sdram_control\sdram_control\sim\work\altddio_bidir\_primary.dat 1533 2005-12-17
sdram_control\sdram_control\sim\work\altddio_bidir\_primary.vhd 1114 2005-12-17
sdram_control\sdram_control\sim\work\altddio_in\verilog.asm 32962 2005-12-17
sdram_control\sdram_control\sim\work\altddio_in\_primary.dat 2388 2005-12-17
sdram_control\sdram_control\sim\work\altddio_in\_primary.vhd 626 2005-12-17
sdram_control\sdram_control\sim\work\altddio_out\verilog.asm 38396 2005-12-17
sdram_control\sdram_control\sim\work\altddio_out\_primary.dat 3016 2005-12-17
sdram_control\sdram_control\sim\work\altddio_out\_primary.vhd 767 2005-12-17
sdram_control\sdram_control\sim\work\altdpram\verilog.asm 73870 2005-12-17
sdram_control\sdram_control\sim\work\altdpram\_primary.dat 5261 2005-12-17
sdram_control\sdram_control\sim\work\altdpram\_primary.vhd 1574 2005-12-17
sdram_control\sdram_control\sim\work\altfp_mult\verilog.asm 145266 2005-12-17
sdram_control\sdram_control\sim\work\altfp_mult\_primary.dat 11359 2005-12-17
sdram_control\sdram_control\sim\work\altfp_mult\_primary.vhd 978 2005-12-17
sdram_control\sdram_control\sim\work\altlvds_rx\verilog.asm 215349 2005-12-17
sdram_control\sdram_control\sim\work\altlvds_rx\_primary.dat 16007 2005-12-17
sdram_control\sdram_control\sim\work\altlvds_rx\_primary.vhd 2132 2005-12-17
sdram_control\sdram_control\sim\work\altlvds_tx\verilog.asm 197331 2005-12-17
sdram_control\sdram_control\sim\work\altlvds_tx\_primary.dat 13552 2005-12-17
sdram_control\sdram_control\sim\work\altlvds_tx\_primary.vhd 1384 2005-12-17
sdram_control\sdram_control\sim\work\altmult_accum\verilog.asm 549177 2005-12-17
sdram_control\sdram_control\sim\work\altmult_accum\_primary.dat 30554 2005-12-17
sdram_control\sdram_control\sim\work\altmult_accum\_primary.vhd 4628 2005-12-17
sdram_control\sdram_control\sim\work\altmult_add\verilog.asm 824059 2005-12-17
sdram_control\sdram_control\sim\work\altmult_add\_primary.dat 46883 2005-12-17
sdram_control\sdram_control\sim\work\altmult_add\_primary.vhd 6168 2005-12-17
sdram_control\sdram_control\sim\work\altpll\verilog.asm 176625 2005-12-17
sdram_control\sdram_control\sim\work\altpll\_primary.dat 18840 2005-12-17
sdram_control\sdram_control\sim\work\altpll\_primary.vhd 10244 2005-12-17
sdram_control\sdram_control\sim\work\altqpram\verilog.asm 249390 2005-12-17
sdram_control\sdram_control\sim\work\altqpram\_primary.dat 17014 2005-12-17
sdram_control\sdram_control\sim\work\altqpram\_primary.vhd 2994 2005-12-17
sdram_control\sdram_control\sim\work\altshift_taps\verilog.asm 23147 2005-12-17
sdram_control\sdram_control\sim\work\altshift_taps\_primary.dat 1287 2005-12-17
sdram_control\sdram_control\sim\work\altshift_taps\_primary.vhd 626 2005-12-17
sdram_control\sdram_control\sim\work\altsqrt\verilog.asm 35527 2005-12-17
sdram_control\sdram_control\sim\work\altsqrt\_primary.dat 2741 2005-12-17
sdram_control\sdram_control\sim\work\altsqrt\_primary.vhd 643 2005-12-17
sdram_control\sdram_control\sim\work\altsyncram\verilog.asm 271908 2005-12-17
sdram_control\sdram_control\sim\work\altsyncram\_primary.dat 18590 2005-12-17
sdram_control\sdram_control\sim\work\altsyncram\_primary.vhd 2854 2005-12-17
sdram_control\sdram_control\sim\work\alt_exc_dpram\verilog.asm 43984 2005-12-17
sdram_control\sdram_control\sim\work\alt_exc_dpram\_primary.dat 3634 2005-12-17
sdram_control\sdram_control\sim\work\alt_exc_dpram\_primary.vhd 1046 2005-12-17
sdram_control\sdram_control\sim\work\alt_exc_upcore\verilog.asm 267975 2005-12-17
sdram_control\sdram_control\sim\work\alt_exc_upcore\_primary.dat 30006 2005-12-17
sdram_control\sdram_control\sim\work\alt_exc_upcore\_primary.vhd 4971 2005-12-17
sdram_control\sdram_control\sim\work\arm_m_cntr\verilog.asm 8450 2005-12-17
sdram_control\sdram_control\sim\work\arm_m_cntr\_primary.dat 851 2005-12-17
sdram_control\sdram_control\sim\work\arm_m_cntr\_primary.vhd 414 2005-12-17
sdram_control\sdram_control\sim\work\arm_n_cntr\verilog.asm 6430 2005-12-17

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