文件名称:DesVer
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实现FPGA中执行DES算法，通过RS232实现数据传送功能 -Implement FPGA DES algorithm is d, data transfer function via RS232
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下载文件列表
DesVer
......\Des.cr.mti
......\Des.mpf
......\Des.v
......\IP.v
......\IP_ni.v
......\Modelsim_10[neubt]Modelsim_se_10.0a_Crackerworkspacewin64worka.txt
......\contrl.v
......\des_f.v
......\des_top.v
......\key_get.v
......\pc_1.v
......\s1.v
......\s2.v
......\s3.v
......\s4.v
......\s5.v
......\s6.v
......\s7.v
......\s8.v
......\testbench.v
......\vsim.wlf
......\work
......\....\@des
......\....\....\_primary.dat
......\....\....\_primary.dbs
......\....\....\_primary.vhd
......\....\@i@p
......\....\....\_primary.dat
......\....\....\_primary.dbs
......\....\....\_primary.vhd
......\....\....\verilog.asm64
......\....\....\verilog.rw64
......\....\@i@p_ni
......\....\.......\_primary.dat
......\....\.......\_primary.dbs
......\....\.......\_primary.vhd
......\....\.......\verilog.asm64
......\....\.......\verilog.rw64
......\....\_info
......\....\_temp
......\....\.....\vlog2b2xgf
......\....\.....\vlog3ej8t4
......\....\.....\vlogt34zny
......\....\_vmake
......\....\ck
......\....\..\_primary.dat
......\....\..\_primary.dbs
......\....\..\_primary.vhd
......\....\contrl
......\....\......\_primary.dat
......\....\......\_primary.dbs
......\....\......\_primary.vhd
......\....\......\verilog.asm64
......\....\......\verilog.rw64
......\....\des_f
......\....\.....\_primary.dat
......\....\.....\_primary.dbs
......\....\.....\_primary.vhd
......\....\.....\verilog.asm64
......\....\.....\verilog.rw64
......\....\des_top
......\....\.......\_primary.dat
......\....\.......\_primary.dbs
......\....\.......\_primary.vhd
......\....\.......\verilog.asm64
......\....\.......\verilog.rw64
......\....\key_get
......\....\.......\_primary.dat
......\....\.......\_primary.dbs
......\....\.......\_primary.vhd
......\....\.......\verilog.asm64
......\....\.......\verilog.rw64
......\....\my_uart_rx
......\....\..........\_primary.dat
......\....\..........\_primary.dbs
......\....\..........\_primary.vhd
......\....\my_uart_tx
......\....\..........\_primary.dat
......\....\..........\_primary.dbs
......\....\..........\_primary.vhd
......\....\pc_1
......\....\....\_primary.dat
......\....\....\_primary.dbs
......\....\....\_primary.vhd
......\....\....\verilog.asm64
......\....\....\verilog.rw64
......\....\s1
......\....\..\_primary.dat
......\....\..\_primary.dbs
......\....\..\_primary.vhd
......\....\..\verilog.asm64
......\....\..\verilog.rw64
......\....\s2
......\....\..\_primary.dat
......\....\..\_primary.dbs
......\....\..\_primary.vhd
......\....\..\verilog.asm64
......\....\..\verilog.rw64
......\....\s3