文件名称:UART
- 所属分类：
- 串口编程
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2013-04-25
- 文件大小：
- 1.09mb
- 下载次数：
- 0次
- 提 供 者：
- zhuku*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
UART --串口发送与接收verilog代码，适用于QUATUS II 开发环境下，适合verilog入门的学员-UART- on serial port ,send and receive signal, suitable for QUATUS II development environment for Verilog entry students
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UART\Doc\sscom.ini
....\...\sscom32.exe
....\...\UART控制器设计说明.doc
....\...\xapp341.pdf
....\func_sim\rcvr.v
....\........\transcript
....\........\txmit.v
....\........\txmit_tf.do
....\........\uart.cr.mti
....\........\uart.mpf
....\........\uart.v
....\........\uart_if.v
....\........\uart_tb.do
....\........\uart_tb.v
....\........\uart_tb_fixed.do
....\........\vish_stacktrace.vstf
....\........\vsim.wlf
....\........\wave.do
....\........\.ork\@u@a@r@t_tb\verilog.asm
....\........\....\...........\_primary.dat
....\........\....\...........\_primary.vhd
....\........\....\rcvr\verilog.asm
....\........\....\....\_primary.dat
....\........\....\....\_primary.vhd
....\........\....\txmit\verilog.asm
....\........\....\.....\_primary.dat
....\........\....\.....\_primary.vhd
....\........\....\uart\verilog.asm
....\........\....\....\_primary.dat
....\........\....\....\_primary.vhd
....\........\....\...._if\verilog.asm
....\........\....\.......\_primary.dat
....\........\....\.......\_primary.vhd
....\........\....\_info
....\physical\altclklock0.bsf
....\........\altclklock0.v
....\........\altclklock0_bb.v
....\........\async_transmitter.bsf
....\........\cmp_state.ini
....\........\db\altsyncram_2dq.tdf
....\........\..\altsyncram_8tj.tdf
....\........\..\altsyncram_9un.tdf
....\........\..\altsyncram_eh31.tdf
....\........\..\altsyncram_g5q.tdf
....\........\..\cntr_cs6.tdf
....\........\..\cntr_gs6.tdf
....\........\..\cntr_ub7.tdf
....\........\..\cntr_vt6.tdf
....\........\..\uart_if.db_info
....\........\..\uart_if.sld_design_entry.sci
....\........\..\uart_if_cmp.qrpt
....\........\..\uart_if_hier_info
....\........\..\uart_if_syn_hier_info
....\........\div.bsf
....\........\div_2.bsf
....\........\div_2.v
....\........\filter.bsf
....\........\LED_flush.bsf
....\........\rcvr.bsf
....\........\simulation\modelsim\cyclone_atoms.v
....\........\..........\........\uart_if.vo
....\........\..........\........\uart_if_modelsim.xrf
....\........\..........\........\uart_if_v.sdo
....\........\..........\........\uart_post.cr.mti
....\........\..........\........\uart_post.mpf
....\........\..........\........\vsim.wlf
....\........\..........\........\work\@p@r@i@m_@d@f@f@e\verilog.asm
....\........\..........\........\....\.................\_primary.dat
....\........\..........\........\....\.................\_primary.vhd
....\........\..........\........\....\.u@a@r@t_tb\verilog.asm
....\........\..........\........\....\...........\_primary.dat
....\........\..........\........\....\...........\_primary.vhd
....\........\..........\........\....\and1\verilog.asm
....\........\..........\........\....\....\_primary.dat
....\........\..........\........\....\....\_primary.vhd
....\........\..........\........\....\....6\verilog.asm
....\........\..........\........\....\.....\_primary.dat
....\........\..........\........\....\.....\_primary.vhd
....\........\..........\........\....\b17mux21\verilog.asm
....\........\..........\........\....\........\_primary.dat
....\........\..........\........\....\........\_primary.vhd
....\........\..........\........\....\.5mux21\verilog.asm
....\........\..........\........\....\.......\_primary.dat
....\........\..........\........\....\.......\_primary.vhd
....\........\..........\........\....\.mux21\verilog.asm
....\........\..........\........\....\......\_primary.dat
....\........\..........\........\....\......\_primary.vhd
....\........\..........\........\....\cyclone_asmiblock\verilog.asm
....\........\..........\........\....\.................\_primary.dat
....\........\..........\........\....\.................\_primary.vhd
....\........\..........\........\....\..........ynch_io\verilog.asm
....\........\..........\........\....\.................\_primary.dat
....\........\..........\........\....\.................\_primary.vhd
....\........\..........\........\....\...............lcell\verilog.asm
....\........\..........\........\....\....................\_primary.dat
....\........\..........\........\....\....................\_primary.vhd
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