文件名称:XAPP454

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 194kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • i**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

Spartan3a MIG user interface
(系统自动生成,下载前可以参看下载内容)

下载文件列表

464\verilog

...\.......\par

...\.......\...\ddr2_test.ucf

...\.......\rtl

...\.......\...\addr_gen.v

...\.......\...\cal_ctl.v

...\.......\...\cal_top.v

...\.......\...\clk_dcm.v

...\.......\...\cmd_fsm.v

...\.......\...\cmp_data.v

...\.......\...\controller.v

...\.......\...\controller_iobs.v

...\.......\...\data_path.v

...\.......\...\data_path_iobs.v

...\.......\...\data_path_rst.v

...\.......\...\data_read.v

...\.......\...\data_read_controller.v

...\.......\...\data_write.v

...\.......\...\ddr2_dm.v

...\.......\...\ddr2_test.v

...\.......\...\ddr2_test_bench.v

...\.......\...\ddr2_top.v

...\.......\...\defines.v

...\.......\...\dqs_delay.v

...\.......\...\fifo_0_wr_en.v

...\.......\...\fifo_1_wr_en.v

...\.......\...\glbl.v

...\.......\...\infrastructure.v

...\.......\...\infrastructure_iobs.v

...\.......\...\iobs.v

...\.......\...\lfsr32.v

...\.......\...\mybufg.v

...\.......\...\prem.v

...\.......\...\rd_gray_ctr.v

...\.......\...\r_w_dly.v

...\.......\...\s3_ddr_iob.v

...\.......\...\s3_dqs_iob.v

...\.......\...\spartan3.v

...\.......\...\tap_dly.v

...\.......\...\wr_gray_ctr.v

...\.......\synth

...\.......\.....\ddr1_test.prj

...\vhdl

...\....\par

...\....\...\ddr2_test.ucf

...\....\rtl

...\....\...\addr_gen.vhd

...\....\...\cal_ctl.vhd

...\....\...\cal_top.vhd

...\....\...\clk_dcm.vhd

...\....\...\cmd_fsm.vhd

...\....\...\cmp_data.vhd

...\....\...\cntrl_display.vhd

...\....\...\controller.vhd

...\....\...\controller_iobs.vhd

...\....\...\datapath_iobs.vhd

...\....\...\data_path.vhd

...\....\...\data_path_rst.vhd

...\....\...\data_read.vhd

...\....\...\data_read_controller.vhd

...\....\...\data_write.vhd

...\....\...\ddr2_dm.vhd

...\....\...\ddr2_dqs_div.vhd

...\....\...\ddr2_test.vhd

...\....\...\ddr2_test_bench.vhd

...\....\...\ddr2_top.vhd

...\....\...\dqs_delay.vhd

...\....\...\fifo_0_wr_en.vhd

...\....\...\fifo_1_wr_en.vhd

...\....\...\glbl.v

...\....\...\infrastructure.vhd

...\....\...\infrastructure_iobs.vhd

...\....\...\iobs.vhd

...\....\...\lfsr32.vhd

...\....\...\mybufg.vhd

...\....\...\parameter.vhd

...\....\...\rd_gray_cntr.vhd

...\....\...\r_w_dly.vhd

...\....\...\s3_ddr_iob.vhd

...\....\...\s3_dqs_iob.vhd

...\....\...\spartan3.v

...\....\...\spartan3.vhd

...\....\...\tap_dly.vhd

...\....\...\wr_gray_cntr.vhd

...\....\synth

...\....\.....\ddr1_test.prj

464

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