文件名称:vga_sim
介绍说明－－下载内容均来自于网络，请自行研究使用
一个简单的VGA界面的设计。能正确通过仿真，并以YUVViewer展示的界面。上板调试成功，能正确显示在VGA上。
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 31767662vga_sim.rar 列表 vga_sim_example\tools\YUVviewerPlus.exe vga_sim_example\tools\yuv.dat vga_sim_example\tools\trans.exe vga_sim_example\tools\trans.c vga_sim_example\src\svga_top.v vga_sim_example\src\svga_dcm.v vga_sim_example\src\svga_data.v vga_sim_example\src\svga_ctrl.v vga_sim_example\sim\work1\tb_svga\_primary.vhd vga_sim_example\sim\work1\tb_svga\_primary.dat vga_sim_example\sim\work1\svga_top\_primary.vhd vga_sim_example\sim\work1\svga_top\_primary.dat vga_sim_example\sim\work1\svga_dcm\_primary.vhd vga_sim_example\sim\work1\svga_dcm\_primary.dat vga_sim_example\sim\work1\svga_data\_primary.vhd vga_sim_example\sim\work1\svga_data\_primary.dat vga_sim_example\sim\work1\svga_ctrl\_primary.vhd vga_sim_example\sim\work1\svga_ctrl\_primary.dat vga_sim_example\sim\work1\_opt\work_tb_svga_fast.dt2 vga_sim_example\sim\work1\_opt\work_tb_svga_fast.asm vga_sim_example\sim\work1\_opt\work_svga_top_fast.dt2 vga_sim_example\sim\work1\_opt\work_svga_top_fast.asm vga_sim_example\sim\work1\_opt\work_svga_dcm_fast.dt2 vga_sim_example\sim\work1\_opt\work_svga_dcm_fast.asm vga_sim_example\sim\work1\_opt\work_svga_data_fast.dt2 vga_sim_example\sim\work1\_opt\work_svga_data_fast.asm vga_sim_example\sim\work1\_opt\work_svga_ctrl_fast.dt2 vga_sim_example\sim\work1\_opt\work_svga_ctrl_fast.asm vga_sim_example\sim\work1\_opt\work__info vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_maximum_period_check_fast__1.dt2 vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_maximum_period_check_fast__1.asm vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_maximum_period_check_fast.dt2 vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_maximum_period_check_fast.asm vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_clock_lost_fast.dt2 vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_clock_lost_fast.asm vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_clock_divide_by_2_fast.dt2 vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_clock_divide_by_2_fast.asm vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver__info vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@i@b@u@f@g_fast.dt2 vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@i@b@u@f@g_fast.asm vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@d@c@m_fast.dt2 vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@d@c@m_fast.asm vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@b@u@f@g_fast.dt2 vga_sim_example\sim\work1\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@b@u@f@g_fast.asm vga_sim_example\sim\work1\_opt\_deps vga_sim_example\sim\work1\_info vga_sim_example\sim\work\tb_svga\_primary.vhd vga_sim_example\sim\work\tb_svga\_primary.dat vga_sim_example\sim\work\svga_top\_primary.vhd vga_sim_example\sim\work\svga_top\_primary.dat vga_sim_example\sim\work\svga_dcm\_primary.vhd vga_sim_example\sim\work\svga_dcm\_primary.dat vga_sim_example\sim\work\svga_data\_primary.vhd vga_sim_example\sim\work\svga_data\_primary.dat vga_sim_example\sim\work\svga_ctrl\_primary.vhd vga_sim_example\sim\work\svga_ctrl\_primary.dat vga_sim_example\sim\work\_opt\work_tb_svga_fast.dt2 vga_sim_example\sim\work\_opt\work_tb_svga_fast.asm vga_sim_example\sim\work\_opt\work_svga_top_fast.dt2 vga_sim_example\sim\work\_opt\work_svga_top_fast.asm vga_sim_example\sim\work\_opt\work_svga_dcm_fast.dt2 vga_sim_example\sim\work\_opt\work_svga_dcm_fast.asm vga_sim_example\sim\work\_opt\work_svga_data_fast.dt2 vga_sim_example\sim\work\_opt\work_svga_data_fast.asm vga_sim_example\sim\work\_opt\work_svga_ctrl_fast.dt2 vga_sim_example\sim\work\_opt\work_svga_ctrl_fast.asm vga_sim_example\sim\work\_opt\work__info vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_maximum_period_check_fast__1.dt2 vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_maximum_period_check_fast__1.asm vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_maximum_period_check_fast.dt2 vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_maximum_period_check_fast.asm vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_clock_lost_fast.dt2 vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_clock_lost_fast.asm vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_clock_divide_by_2_fast.dt2 vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_dcm_clock_divide_by_2_fast.asm vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver__info vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@i@b@u@f@g_fast.dt2 vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@i@b@u@f@g_fast.asm vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@d@c@m_fast.dt2 vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@d@c@m_fast.asm vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@b@u@f@g_fast.dt2 vga_sim_example\sim\work\_opt\_opt_xilinx_Xilinx92i_verilog_mti_se_unisims_ver_@b@u@f@g_fast.asm vga_sim_example\sim\work\_opt\_deps vga_sim_example\sim\work\_info vga_sim_example\sim\wlftz94TJJ vga_sim_example\sim\wlftuJ3wT9 vga_sim_example\sim\wlftTVfVRp vga_sim_example\sim\wlftrM4T6k vga_sim_example\sim\wlftf5YdiM vga_sim_example\sim\wlftcfiKWi vga_sim_example\sim\vsim.wlf vga_sim_example\sim\transcript vga_sim_example\sim\sim.do~ vga_sim_example\sim\sim.do vga_sim_example\sim\run.f vga_sim_example\sim\modelsim.ini vga_sim_example\sim\makefile vga_sim_example\data\red.dat vga_sim_example\data\green.dat vga_sim_example\data\blue.dat vga_sim_example\bench\tb_svga.v vga_sim_example\sim\work1\tb_svga vga_sim_example\sim\work1\svga_top vga_sim_example\sim\work1\svga_dcm vga_sim_example\sim\work1\svga_data vga_sim_example\sim\work1\svga_ctrl vga_sim_example\sim\work1\_temp vga_sim_example\sim\work1\_opt vga_sim_example\sim\work\tb_svga vga_sim_example\sim\work\svga_top vga_sim_example\sim\work\svga_dcm vga_sim_example\sim\work\svga_data vga_sim_example\sim\work\svga_ctrl vga_sim_example\sim\work\_temp vga_sim_example\sim\work\_opt vga_sim_example\sim\work1 vga_sim_example\sim\work vga_sim_example\tools vga_sim_example\src vga_sim_example\sim vga_sim_example\data vga_sim_example\bench vga_sim_example