文件名称:IIC_ISE_FPGA
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
IIC在fpga中的实现。完整的ISE工程文件-IIC is implemented in fpga.Complete the ISE project file.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
IIC_ISE_FPGA\automake.log
............\coregen.log
............\coregen.prj
............\I2C.dhp
............\I2C.npl
............\i2c_master_bit_ctrl.cmd_log
............\i2c_master_bit_ctrl.lso
............\i2c_master_bit_ctrl.ngc
............\i2c_master_bit_ctrl.ngr
............\i2c_master_bit_ctrl.prj
............\i2c_master_bit_ctrl.stx
............\i2c_master_bit_ctrl.syr
............\i2c_master_bit_ctrl.v
............\i2c_master_bit_ctrl.v.bak
............\i2c_master_bit_ctrl_vhdl.prj
............\i2c_master_byte_ctrl.cmd_log
............\i2c_master_byte_ctrl.lso
............\i2c_master_byte_ctrl.ngc
............\i2c_master_byte_ctrl.ngr
............\i2c_master_byte_ctrl.prj
............\i2c_master_byte_ctrl.stx
............\i2c_master_byte_ctrl.syr
............\i2c_master_byte_ctrl.v
............\i2c_master_byte_ctrl.v.bak
............\i2c_master_byte_ctrl_vhdl.prj
............\i2c_master_defines.v
............\i2c_master_defines.v.bak
............\i2c_master_top.cmd_log
............\i2c_master_top.lso
............\i2c_master_top.ngc
............\i2c_master_top.ngr
............\i2c_master_top.prj
............\i2c_master_top.stx
............\i2c_master_top.syr
............\i2c_master_top.v
............\i2c_master_top.v.bak
............\i2c_master_top_vhdl.prj
............\i2c_slave_model.fdo
............\i2c_slave_model.ndo
............\i2c_slave_model.udo
............\i2c_slave_model.v
............\i2c_slave_model.v.bak
............\prjname.lso
............\timescale.v
............\transcript
............\tst_bench_top.v
............\wb_master_model.v
............\wb_master_model.v.bak
............\.ork\glbl\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\glbl
............\....\i2c_slave_model\verilog.asm
............\....\...............\_primary.dat
............\....\...............\_primary.vhd
............\....\i2c_slave_model
............\....\_info
............\work
............\xst\work\hdllib.ref
............\...\....\vlg07\i2c_master_bit_ctrl.bin
............\...\....\vlg07
............\...\....\...5C\i2c_master_byte_ctrl.bin
............\...\....\vlg5C
............\...\....\...67\i2c_master_top.bin
............\...\....\vlg67
............\...\work
............\xst
............\__projnav\coregen.rsp
............\.........\I2C.gfl
............\.........\I2C_flowplus.gfl
............\.........\i2c_master_bit_ctrl.xst
............\.........\i2c_master_byte_ctrl.xst
............\.........\i2c_master_top.xst
............\.........\runXst_tcl.rsp
............\.........\xst_sprjTOstx_tcl.rsp
............\__projnav
............\__projnav.log
IIC_ISE_FPGA
............\coregen.log
............\coregen.prj
............\I2C.dhp
............\I2C.npl
............\i2c_master_bit_ctrl.cmd_log
............\i2c_master_bit_ctrl.lso
............\i2c_master_bit_ctrl.ngc
............\i2c_master_bit_ctrl.ngr
............\i2c_master_bit_ctrl.prj
............\i2c_master_bit_ctrl.stx
............\i2c_master_bit_ctrl.syr
............\i2c_master_bit_ctrl.v
............\i2c_master_bit_ctrl.v.bak
............\i2c_master_bit_ctrl_vhdl.prj
............\i2c_master_byte_ctrl.cmd_log
............\i2c_master_byte_ctrl.lso
............\i2c_master_byte_ctrl.ngc
............\i2c_master_byte_ctrl.ngr
............\i2c_master_byte_ctrl.prj
............\i2c_master_byte_ctrl.stx
............\i2c_master_byte_ctrl.syr
............\i2c_master_byte_ctrl.v
............\i2c_master_byte_ctrl.v.bak
............\i2c_master_byte_ctrl_vhdl.prj
............\i2c_master_defines.v
............\i2c_master_defines.v.bak
............\i2c_master_top.cmd_log
............\i2c_master_top.lso
............\i2c_master_top.ngc
............\i2c_master_top.ngr
............\i2c_master_top.prj
............\i2c_master_top.stx
............\i2c_master_top.syr
............\i2c_master_top.v
............\i2c_master_top.v.bak
............\i2c_master_top_vhdl.prj
............\i2c_slave_model.fdo
............\i2c_slave_model.ndo
............\i2c_slave_model.udo
............\i2c_slave_model.v
............\i2c_slave_model.v.bak
............\prjname.lso
............\timescale.v
............\transcript
............\tst_bench_top.v
............\wb_master_model.v
............\wb_master_model.v.bak
............\.ork\glbl\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\glbl
............\....\i2c_slave_model\verilog.asm
............\....\...............\_primary.dat
............\....\...............\_primary.vhd
............\....\i2c_slave_model
............\....\_info
............\work
............\xst\work\hdllib.ref
............\...\....\vlg07\i2c_master_bit_ctrl.bin
............\...\....\vlg07
............\...\....\...5C\i2c_master_byte_ctrl.bin
............\...\....\vlg5C
............\...\....\...67\i2c_master_top.bin
............\...\....\vlg67
............\...\work
............\xst
............\__projnav\coregen.rsp
............\.........\I2C.gfl
............\.........\I2C_flowplus.gfl
............\.........\i2c_master_bit_ctrl.xst
............\.........\i2c_master_byte_ctrl.xst
............\.........\i2c_master_top.xst
............\.........\runXst_tcl.rsp
............\.........\xst_sprjTOstx_tcl.rsp
............\__projnav
............\__projnav.log
IIC_ISE_FPGA