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[软件工程] verilog workshop
说明:Verilog/SystemVerilog for Design and Synthesis is a comprehensive workshop covering the complete Verilog Hardware Descr iption Language and the synthesizable portions of SystemVerilog, including user-defined types, enume<santoshJadhav> 在 2025-04-07 上传 | 大小:991kb | 下载:0
[软件工程] 3-spice
说明:SPICE (Simulation Program with Integrated Circuit Emphasis) is a general-purpose, open source analog electronic circuit simulator.<santoshJadhav> 在 2025-04-07 上传 | 大小:276kb | 下载:0
[编程文档] DP-BPSK transmission
说明:optiwave bpsk model transmission<ash1122> 在 2025-04-07 上传 | 大小:119kb | 下载:0
[文档资料] C++LBM顶盖驱动流
说明:模拟顶盖驱动流,为LBM模型下的纯流动情况(thanks for helping you)<LeoYang8> 在 2025-04-07 上传 | 大小:21kb | 下载:0