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[书籍源码] SDRAM_interface
说明:SDRAM verilog 代码,已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to ref<bryan> 在 2025-04-29 上传 | 大小:2kb | 下载:0
[书籍源码] Two-layer-support-vector-machine
说明:Two layer support vector machine<他里雾> 在 2025-04-29 上传 | 大小:2kb | 下载:0
[书籍源码] ofdm_fading
说明:simulation systerm ofdma in ebook Simulation and Software Radio for Mobile Communications<hellomoto> 在 2025-04-29 上传 | 大小:2kb | 下载:0