资源列表

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[邮电通讯系统Multipath

说明:3GPP wireless communications multipath channel
<achs> 在 2024-11-02 上传 | 大小:1024 | 下载:0

[邮电通讯系统FastFading

说明:3GPP wireless communications systems
<achs> 在 2024-11-02 上传 | 大小:1024 | 下载:0

[邮电通讯系统SCM

说明:SCM space channel Model for 3G-SCM space channel Model for 3GPP
<achs> 在 2024-11-02 上传 | 大小:1024 | 下载:0

[邮电通讯系统Tw2835code

说明:tecwell 2835 motion function 初始化及設定值 4channel 輸入 motion ebable-tecwell 2835 motion function to initialize and set the value of motion ebable input 4channel
<黃志平> 在 2024-11-02 上传 | 大小:123904 | 下载:0

[邮电通讯系统UAR_sound_control

说明:La estupida evaluacion heuristica
<juan> 在 2024-11-02 上传 | 大小:582656 | 下载:0

[邮电通讯系统YD-T_1363.3-2005

说明:YD-T_1363.3-2005_通信局(站)电源、空调及环境集中监控管理系统第3部分:前端智能设备协议-YD-T_1363.3-2005_ Communications Authority (station) power supply, air-conditioning and environmental monitoring and management systems focus on Part 3: intelligent fr
<anono> 在 2024-11-02 上传 | 大小:4998144 | 下载:0

[邮电通讯系统YD-T_1363.4-2005

说明:YD-T_1363.4-2005_通信局(站)电源、空调及环境集中监控管理系统第4部分:测试方法-YD-T_1363.4-2005_ Communications Authority (station) power supply, air-conditioning and environmental management system for centralized monitoring Part 4: Test Methods
<anono> 在 2024-11-02 上传 | 大小:1579008 | 下载:0

[邮电通讯系统gcl.src.tar

说明:BOI version of Steiner tree construction, practical and popular for manhattan VLSI routing, generate a Steiner minimum tree for given set of terminals in a layout plane-BOI version of Steiner tree construction, practical
<Ernesto Liu> 在 2024-11-02 上传 | 大小:365568 | 下载:0

[邮电通讯系统PTree.tar

说明:PTree: Find the optimum Steiner tree for a given terminal sequence. Linear runtime complexity. Optimum solution.
<Ernesto Liu> 在 2024-11-02 上传 | 大小:140288 | 下载:0

[邮电通讯系统buf_tree_pol.tar

说明:Construct buffered routing tree for VLSI interconnects in a Manhanttan layout plane for a given set of terminals, guarantee polarity of the terminals agree with each other
<Ernesto Liu> 在 2024-11-02 上传 | 大小:33792 | 下载:0

[邮电通讯系统Minaret.tar

说明:Minaret: retiming edge-triggered circuit for improved performance and higher clock frequency by moving combinational logic gates across sequential elements
<Ernesto Liu> 在 2024-11-02 上传 | 大小:2823168 | 下载:0

[邮电通讯系统FengShui.tar

说明:FengShui: custom ASIC layout placement for gigascale VLSI circuits, for gate array, sea of gate and standard cell designs, scales well into million gate designs-FengShui: custom ASIC layout placement for gigascale VLSI
<Ernesto Liu> 在 2024-11-02 上传 | 大小:584704 | 下载:0
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