资源列表
[VHDL编程] usb_phy.tar
说明:Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX se<eldis> 在 2025-01-22 上传 | 大小:7kb | 下载:0
[VHDL编程] simple_spi.tar
说明:Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer<eldis> 在 2025-01-22 上传 | 大小:561kb | 下载:0
[VHDL编程] mcpu_1.06b
说明:MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable<eldis> 在 2025-01-22 上传 | 大小:243kb | 下载:0
[VHDL编程] usart_verilog
说明:Uart verilog 代码 可综合 很好的代码-Uart verilog code<shenhao> 在 2025-01-22 上传 | 大小:15kb | 下载:0
[VHDL编程] rd_wr_control
说明:USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.<Somasekhar> 在 2025-01-22 上传 | 大小:1kb | 下载:0
[VHDL编程] tx_buff
说明:USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.<Somasekhar> 在 2025-01-22 上传 | 大小:1kb | 下载:0
[VHDL编程] rec_buf
说明:USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.<Somasekhar> 在 2025-01-22 上传 | 大小:2kb | 下载:0
[VHDL编程] usart
说明:USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.<Somasekhar> 在 2025-01-22 上传 | 大小:1kb | 下载:0
[VHDL编程] HDB3
说明:hdb3的编解码实现,用c表述的 实际应用性不强,只为说明原理。-HDB3 codec realize, with the practical application of c expression is not strong, only to illustrate the principle.<lixingjian> 在 2025-01-22 上传 | 大小:188kb | 下载:0
[VHDL编程] DE2_NIOS_Lite_12_flash
说明:实现如何在Nios II对Flash进行读写 [SOPC、Nios II、DE2] -Introduce how to read and write the Flash using Nios II[SOPC、Nios II、DE2]<bobgeng> 在 2025-01-22 上传 | 大小:1.05mb | 下载:0
[VHDL编程] 75448172geleicounter
说明:这是异步fifo的vhdl实现代码,已经在FPGA上通过实践证明,运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition<xzq> 在 2025-01-22 上传 | 大小:1kb | 下载:0