[单片机(51,AVR,MSP430等)] Capacitive-Touch-Pad-SegLCD

说明：这是一个有MSP430FG4618实验板做成的电容触摸按键程序，其中触摸按键由IIc协议从从机MSP430F2013读出，然后送到LCD显示- A program for the MSP430FG4618 on the Experimenter s board to accept I2C information from the touchpad, display it numerically on the LCD, and send
<顶顶> 在 2025-02-28 上传 | 大小：2.1mb | 下载：0

[单片机(51,AVR,MSP430等)] Wireless-interface-using-MSP430

说明：本实验针对 CC1100 和CC2500，演示简单的通讯过程，通过按键无线控制LED 的亮灭。本实验板是华凡的MSPFG4618实验板。-In this study, for CC1100 and CC2500, demonstrate a simple communication process, by controlling the LED light button wireless off. In this study, wher
<顶顶> 在 2025-02-28 上传 | 大小：300kb | 下载：0

[VHDL编程] I2C_vhdl

说明： IMPORTANT NOTE: This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this sign
<vijendra pal> 在 2025-02-28 上传 | 大小：830kb | 下载：0

[VHDL编程] manchester_verilog

说明： This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
<vijendra pal> 在 2025-02-28 上传 | 大小：10kb | 下载：0

[VHDL编程] manchester_vhdl

说明：This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
<vijendra pal> 在 2025-02-28 上传 | 大小：11kb | 下载：0

[VHDL编程] spi_cpld_vhdl

说明：The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified
<vijendra pal> 在 2025-02-28 上传 | 大小：431kb | 下载：0

[VHDL编程] uart_verilog

说明：The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL
<vijendra pal> 在 2025-02-28 上传 | 大小：5kb | 下载：0

[VHDL编程] uart_vhdl

说明：The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL
<vijendra pal> 在 2025-02-28 上传 | 大小：6kb | 下载：0

[VHDL编程] smartcard_vhdl

说明：Readme File for Smart Card Reader File Contents ************************************************************************* This zip file contains the following files: -- VHDL Source Files in Smartcard: To
<vijendra pal> 在 2025-02-28 上传 | 大小：515kb | 下载：0

[VHDL编程] project-05

说明：Project05.zip Memory.hdl
<Rosh> 在 2025-02-28 上传 | 大小：13kb | 下载：0

[DSP编程] 21k_asm

说明：analog device ADSP developement tools and descr iption 1
<fau> 在 2025-02-28 上传 | 大小：421kb | 下载：0

[DSP编程] 21k_ccm

说明：analog device ADSP developement tools and descr iption for AD21-analog device ADSP developement tools and descr iption for AD21xx
<fau> 在 2025-02-28 上传 | 大小：2.04mb | 下载：0