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[软件工程] verilog workshop
说明:Verilog/SystemVerilog for Design and Synthesis is a comprehensive workshop covering the complete Verilog Hardware Descr iption Language and the synthesizable portions of SystemVerilog, including user-defined types, enume<santoshJadhav> 在 2025-03-06 上传 | 大小:991kb | 下载:0
[其他小程序] verilog_best
说明:Hardware Descr iption Language and the synthesizable portions of SystemVerilog, including user-defined types, enumerated types, structures, and self-verifying decision statements<santoshJadhav> 在 2025-03-06 上传 | 大小:751kb | 下载:0
[Dephi控件源码] eUpdator_Delphi
说明:eUpdator is a free system for adding version control to your applications.<pepesilv> 在 2025-03-06 上传 | 大小:60kb | 下载:0
[其他小程序] 3. Comparator
说明:EXCLUSIVE OR and EXCLUSIVE NOR gates may be viewed as 1-bit comparators. Figure 1(a) shows an interpretation of the 74x86 XOR gate as a 1-bit comparator<santoshJadhav> 在 2025-03-06 上传 | 大小:355kb | 下载:0
[软件工程] 3-spice
说明:SPICE (Simulation Program with Integrated Circuit Emphasis) is a general-purpose, open source analog electronic circuit simulator.<santoshJadhav> 在 2025-03-06 上传 | 大小:276kb | 下载:0