搜索资源列表
PLL
- 基于matlab的锁相环（PLL）仿真源代码-Matlab based on the phase-locked loop (PLL) simulation source code
suoxiang
- 该文件运用matlab仿真工具仿真通信中的关键技术之一，锁相环。采用不同的调制方式。-The document the use of simulation tools for communication matlab simulation of one of the key technologies, phase-locked loop. Different modulation.
phase-locked
- 主要是关于锁相环的环路滤波设计与计算，非常经典的-Mainly on the phase-locked loop filter design and calculation, very classic
pll
- 模拟锁相环（apll）的一些simulink模型-Analog phase-locked loop (apll) some simulink model
Pllrrrr
- 锁相环（非科斯塔斯环） 对波动频率进行锁定，并且对信号进行解调。画图7个显示过程及参数-The phase locked loop(PLL),adjusts the phase of a local oscillator.the phase of the incoming signal is locked and the signal is demodulated show the process and reference
suoxianghuan
- 锁相环（PLL）simulink仿真，加深对PLL的理解-Phase-locked loop (PLL) simulink simulation, to deepen understanding of the PLL
MATLAB
- 二阶锁相环 m 文件，运行有图，应用广泛-Second-order phase-locked loop m documents, there are plans to run a wide range
ADPLL
- 全数字锁相环（adpll)的部分源程序代码，是其中最重要的部分。-All-digital phase-locked loop (adpll) part of the source code, is one of the most important part.
PLL
- 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation
simple_pll_3
- 简单的模拟锁相环仿真，基于simulink平台使本地震荡频率跟上接收到得频率-analog pll simulation,based on simulink
pll
- 设计的软件锁相环的例子，自己写的，根据原理编的-PLL design example of software that he wrote, according to the principle for the
pll_verilog
- 全数字锁相环的verilog源代码,仿真已通过 -All-Digital Phase-Locked Loop verilog source code, simulation has passed
PLL
- 用VHDL和matlab编写的数字锁相环电路。-Matlab with VHDL and digital phase-locked loop circuit prepared.
SUOXIANG222
- 锁相环的MATLAB SIMULINK编程，可以供研究锁相环的人员使用-MATLAB SIMULINK programming the phase-locked loop, you can study for the use of Phase-Locked Loop
PLL_grt_rtw
- C语言实现了数字锁相环的程序，不过程序比较复杂，得参照MATLAB中 Discrete 3-phase pll模型-C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model
pll
- 摘要:叙述了全数字锁相环的工作原理,提出了应用VHDL 技术设计全数字锁相环的方法,并用复杂可编程逻辑器件CPLD 予以实现,给出了系统主要模块的设计过程和仿真结果。-Abstract: This paper describes the working principle of an all-digital phase-locked loop is proposed application VHDL technical design a
2009
- 智能全数字锁相环的设计,基于FPGA实现。-Intelligent all-digital phase-locked loop design, FPGA-based implementation.
PLL
- LM3236锁相环程序设计-LM3236 PLL program design
PrenticeHallPrincipleofCommunicationSystemSmulatio
- 本书分成三部分，第一部分讨论了仿真的作用和方法论。第二部分介绍了采样定理，滤波器模型、锁相环等的仿真。第三部分是高层建模与仿真方法。-The book is divided into three parts, the first section discusses the role of simulation and methodology. The second part of the sampling theorem, the fi
divde_clk10m
- 一种带负反馈,无见相思曲的高精度锁相环,采用双D触发器实现-PLL