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uart_verilog
- verilog & vhdl以及外国公司的应用说明。-Verilog
uart_verilog
- uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
UART
- UART_verilog,自己设计的异步串行收发。包括测试文件。
uart_verilog
- 简化的串口通信，去掉了奇偶校验位，波特率为9600，测试通过，fpga型号为xinlinx vp20
uart_verilog
- this is a sample about UART transmission,it s default installation is D:\\RedLogic\\RCII_samples, and the software environment is quatrusII 5.0,it is usefull for studying UART.
uart_verilog
- UART接口被广泛应用在程序调适和信息输出。本实验将介绍UART接口的自测和调试实 例，通过这两个实例来掌握UART的设计方法和超级终端使用方法。
uart_verilog
- 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can
uart_verilog-get&send
- verilog语言实现uart的通讯
uart_verilog hdl
- FPGA中串口的实现，基于verilog hdl
uart_verilog
- 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can
uart_verilog_v1
- uart d的verilog 程序，可以实现普通串口功能-UART d Verilog procedures can be achieved ordinary serial port function
uart_verilog
- verilog & vhdl以及外国公司的应用说明。-Verilog
Altera_uart_Verilog
- FPGA/CPLD应用,uart的Verilog HDL原码-FPGA/CPLD applications, UART Verilog HDL source
uart_verilog
- uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
UART
- UART_verilog,自己设计的异步串行收发。包括测试文件。-UART_verilog, designed to send and receive asynchronous serial. Including the test file.
uart_verilog
- 简化的串口通信，去掉了奇偶校验位，波特率为9600，测试通过，fpga型号为xinlinx vp20-Simplified serial communication, removing the parity bit, the baud rate to 9600, test, fpga model xinlinx vp20
uart_verilog
- this is a sample about UART transmission,it s default installation is D:\RedLogic\RCII_samples, and the software environment is quatrusII 5.0,it is usefull for studying UART.-this is a sample about UART transmission, it
uart_verilog
- UART接口被广泛应用在程序调适和信息输出。本实验将介绍UART接口的自测和调试实 例，通过这两个实例来掌握UART的设计方法和超级终端使用方法。-UART interface is widely used in the procedures and information to adjust the output. This experiment will introduce self-UART interface and deb
uart_verilog
- 用verilog编写的标准异步串行通行程序，供大家参考！-Prepared using Verilog standard asynchronous serial passage procedures for your reference!
uart_verilog
- 串口的Verilog源程序，可以用modelsim下进行仿真调试-Serial port of the Verilog source code can be carried out under the modelsim simulation debugging