搜索资源列表
adc_vhdl.tar
- control adc vhdl code spartan 3e starter board
Wiley.FPGA.Prototyping.by.VHDL.Examples.Xilinx.Sp
- Wiley,FPGA Prototyping by VHDL examples Spartan 3 version,Pong Chu,
s3ask_ddr2
- DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit-DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit
fpga-dm9000a
- 一个项目工程，硬件包含XINLINX FPGA，配置FLASH，串口，SDRAM,与以太网芯片DM9000A，实现数据采集，以太网传输，电路验证完全正确，请放心使用，SPARTAN 3E 的BGA引脚320个，不容易布板，可以参考使用的。要FPGA实现网络通信也可以参考电路，B因为产品升级了所以公开原来的电路的。 -A project engineering, hardware contains XINLINX FPGA, config
PCI_t
- PCI 3.3V 設計指南 Xilinx Spartan-3-PCI 3.3V design guide Xilinx Spartan-3
xc_optimize53
- Using Spartan-3/3E Features to Area-Optimize Your Design
s3esk
- spartan 3e开发板的实验例程，包括对应的说明文档-spartan 3e development board test routines, including the corresponding documentation
9956EABFd01
- Spartan-3 FPGA Starter Kit Board
project_spartan2
- this is a spartan 2 project
c_xapp454
- 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese versio
s3esk_startup
- 利用kcpsm3控制lcd显示 平台：ise 10.1， picoblaze， Spartan3e 开发板 说明：综合按键和lcd、led的功能，思想简单，需要新技术，适合想在fpga方面深造的人。-using kcpsm3 for lcd display platform: ise 10.1， picoblaze， Spartan-3E FPGA Starter Kit Board comment: involve
rs232
- rs232 interface for xilinx spartan 3e
lcd
- lcd display on xilinx spartan 3e
ug230
- Xilinx Spartan 3E 实验板详细说明书-Xilinx Spartan 3E board experiments detailed descr iption
s3esk_cpld_design
- Spartan-3E板卡XC2C64A CPLD 的代码-the XC2C64A CPLD on the Spartan-3E Starter Kit boards
s3esk_rotary_encoder_interface
- spartan-3e starter board 旋转开关-spartan-3e starter board rotary push Button
s3esk_startup_lcd
- spartan-3e starter board lcd显示-spartan-3e starter board lcd display
wtut_edif
- Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the cl
clock2Hz
- this fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the pro